View MPC5675K_4351907.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tbd mapbga?225 15 mm x 15 mm qfn12 ##_mm_x_##mm sot-343r ##_mm_x_##mm pkg-tbd ## mm x ## mm 257 mapbga (14 x 14 mm) 473 mapbga (19 x 19 mm) freescale semiconductor data sheet: technical data document number: MPC5675K rev. 7, 5/2012 MPC5675K ? freescale semiconductor, inc., 2009?2012. all rights reserved. 1 introduction 1.1 document overview this document provides el ectrical specifications, pin assignments, and package diagrams for the qorivva MPC5675K series of microcontroller units (mcus). 1.2 description the qorivva MPC5675K microcontroller, a safeassure solution, is a 32-bit embedded controller designed for advanced driver assistance systems with radar, cmos imaging, lidar and ultrasonic sensors, and multiple 3-phase motor control applications as in hybrid electric vehicles (hev) in automotive and high temperature industrial applications. a member of freescale semiconductor?s qorivva mpc5500/5600 family, it contains the book e compliant power architecture ? technology core with variable length encoding (vle). this core complies with the power architecture embedded category, and is 100 percent user mode compatible with the original power pc ? user instruction set architecture (uisa). it offers system performance up to four times that of its mpc5561 predecessor, while bringing you the reliability and familiarity of the proven power architecture technology. a comprehensive suite of hardware and software development tools is available to help simplify and speed system design. development support is available from leading tools vendors providing compilers, debuggers and simulation development environments. qorivva MPC5675K microcontroller data sheet 1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . 17 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 69 3.3 recommended operating conditions . . . . . . . . . . . . . . 70 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 72 3.5 electromagnetic interference (emi) characteristics . . . 73 3.6 electrostatic discharge (esd) characteristics. . . . . . . . 74 3.7 static latch-up (lu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.8 power management controller (pmc) electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.9 supply current characteristics. . . . . . . . . . . . . . . . . . . . 76 3.10 temperature sensor electrical characteristics. . . . . . . . 77 3.11 main oscillator elec trical characteristics . . . . . . . . . . . . 77 3.12 fmpll electrical characteristics . . . . . . . . . . . . . . . . . . 78 3.13 16 mhz rc oscillator electrical characteristics. . . . . . . 79 3.14 adc electrical characteristics . . . . . . . . . . . . . . . . . . . . 79 3.15 flash memory electrical charac teristics . . . . . . . . . . . . 84 3.16 sram memory electrical characteristics . . . . . . . . . . . 86 3.17 gp pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.18 pdi pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 88 3.19 dram pad specifications . . . . . . . . . . . . . . . . . . . . . . . 90 3.20 reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.21 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.22 peripheral timing characteristics . . . . . . . . . . . . . . . . . 102 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.1 package mechanical data. . . . . . . . . . . . . . . . . . . . . . 126 5 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 7 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 132
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 2 1.3 device comparison table 1. MPC5675K family device comparison features mpc5673k mpc5674k MPC5675K cpu type 2 e200z7d (sor 1 ) in lock-step or decoupled operation architecture harvard execution speed 0?150 mhz (+2% fm) 0?180 mhz (+2% fm) 0?180 mhz (+2% fm) nominal platform frequency (in 1:1, 1:2, and 1:3 modes) 0?75 mhz (+2% fm) 0?90 mhz (+2% fm) 0?90 mhz (+2% fm) mmu 64 entries (sor) instruction set ppc yes instruction set vle yes instruction cache 16 kb, 4-way with edc (sor) data cache 16 kb, 4-way with parity (sor) mpu yes (sor) buses core bus 32-bit address, 64-bit data internal periphery bus 32-bit address, 32-bit data xbar master ? slave ports yes (sor) memory static ram (sram) 256 kb (ecc) 384 kb (ecc) 512 kb (ecc) code flash memory 1 mb 2 1.5 mb 2 2mb 2 data flash memory 64 kb 2 modules analog-to-digital converter (adc) 257 pin pkg: 4 12 bit (22 external channels) 473 pin pkg: 4 12 bit (up to 34 external channels) crc unit 2 (3 contexts each) cross triggering unit (ctu) 2 modules deserial serial peripheral interface (dspi) 2 modules (3 chip selects) 3 3 modules 4 digital i/os ? 16 dram controller (dramc) no yes 5 enhanced direct memory access (edma) 2 modules, 32 channels each etimer 3 modules, 6 channels each
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 3 modules (cont.) external bus interface (ebi) 1 module 5 16-bit data + address or 32-bit data with address bus muxed 8 fast ethernet controller (fec) 1 module fault collection and control unit (fccu) 1 module flexcan 4 modules (32 message buffers each) flexpwm 3 modules (each 4 3 channels) flexray optional yes i 2 c 2 modules 6 3 modules interrupt controller (intc) yes (sor) linflex 3 modules 7 4 modules parallel data interface (pdi) 1 module 8 periodic interrupt timer (pit) 1 module, 4 channels software watchdog timer (swt) yes (sor) system timer module (stm) yes (sor) temperature sensor 1 module wakeup unit (wkpu) yes crossbar switch (xbar) 3 modules, 2 are user-configurable clocking clock monitor unit (cmu) 3 modules frequency-modulated phase-locked loop (fmpll) 2 modules (system and auxiliary) ircosc ? 16 mhz 1 xosc 4?40 mhz 1 supply power management unit (pmu) ye s 1.2 v low-voltage detector (lvd12) 1 1.2 v high-voltage detector (hvd12) 1 2.7 v low-voltage detector (lvd27) 4 debug nexus class 3+ (for cores and sram ports) table 1. MPC5675K family device comparison (continued) features mpc5673k mpc5674k MPC5675K
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 4 packages mapbga 257 pins 473 pins temperature ambient see the t a recommended operating condition in the device data sheet 1 sphere of replication. 2 does not include test or shadow flash memory space. 3 dspi_0 and dspi_1. 4 dspi_0 has 8 chip selects; dspi_1 and dspi_2 have 4 chip selects each. 5 available only on 473-pin package. 6 i2c_0 and i2c_1. 7 linflex_0, linflex_1, and linflex_2. 8 ddr available only on 473 package. other modules available as follows: ebi or ddr on 473 package ebi + pdi on 473 package ddr + pdi on 473 package pdi only on 257 package table 1. MPC5675K family device comparison (continued) features mpc5673k mpc5674k MPC5675K
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 5 1.4 block diagram figure 1 shows a top-level block diagram of the MPC5675K device. figure 1. MPC5675K block diagram dma_1 adc ? analog-to-digital converter bam ? boot assist module cmu ? clock monitoring unit crc ? cyclic redundanc y check unit ctu ? cross triggering unit dspi ? deserial serial peripheral interface ebi ? external bus interface ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller fccu ? fault collection and control unit fec ? fast ethernet controller flexcan ? controller area network controller flexpwm ? pulse width modulator module fmpll ? frequency-modulated phase-locked loop i2c ? inter-integrated circuit controller intc ? interrupt controller ircosc ? internal rc oscillator jtag ? joint test action group interface mc ? mode entry, clock, reset, and power modules mddr ? mobile double data rate dynamic ram pbridge ? peripheral bridge pdi ? parallel data interface pit ? periodic interrupt timer pmc ? power management controller rc ? redundancy checker rtc ? real time clock sema4 ? semaphore unit siul ? system integration unit lite sscm ? system status and configuration module stm ? system timer module swt ? software watchdog timer tsens ? temperature sensor xosc ? crystal oscillator ecsm_0 stm intc crossbar switch (xbar_2) crossbar switch (xbar_1) memory protection unit pbridge debug flexray pbridge siul mc wakeup adc adc xosc bam sscm secondary pll fmpll ircosc cmu cmu ctu pit fccu flexpwm flexpwm etimer etimer etimer flexcan flexcan linflex linflex dspi dspi dspi crc cmu sema4 tsens pdi adc adc ctu flexpwm linflex linflex flexcan flexcan ddr controller i 2 c i 2 c i 2 c crc dma_0 ethernet pflashc pflashc sram with ecc logic sram with ecc logic pbridge swt_0 crossbar switch (xbar_0) memory protection unit pmc redundancy checker[6] redundancy checker[3] redundancy checker[4] redundancy checker[2] redundancy checker[5] nexus jtag interface ecsm_1 stm intc sema4 swt_1 pmc external bus 2mb flash with ecc logic d-cache e200z7d core_1 i-cache vle spe2 mmu d-cache e200z7d core_1 i-cache vle spe2 mmu redundancy checker[7] redundancy checker[0]
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 6 1.5 feature list ? high-performance e200z7d dual core ? 32-bit power architecture ? technology cpu ? up to 180 mhz core frequency ? dual-issue core ? variable length encoding (vle) ? memory management unit (mmu) with 64 entries ? 16 kb instruction cache and 16 kb data cache ? memory available ? up to 2 mb code flash memory with ecc ? 64 kb data flash memory with ecc ? up to 512 kb on-chip sram with ecc ? sil3/asild innovative safety concept: lockstep mode and fail-safe protection ? sphere of replication (sor) for key components ? redundancy checking units on outputs of the sor connected to fccu ? fault collection and control unit (fccu) ? boot-time built-in self-test for memory (mbist) and logic (lbist) triggered by hardware ? boot-time built-in self-test for adc and flash memory ? replicated safety-enh anced watchdog timer ? silicon substrate (die) temperature sensor ? non-maskable interrupt (nmi) ? 16-region memory protection unit (mpu) ? clock monitoring units (cmu) ? power management unit (pmu) ? cyclic redundancy check (crc) units ? decoupled parallel mode for high-pe rformance use of replicated cores ? nexus class 3+ interface ? interrupts ? replicated 16-priority interrupt controller ? gpios individually programmable as input, output, or special function ? 3 general-purpose etimer units (6 channels each) ? 3 flexpwm units with four 16-bit channels per module ? communications interfaces ? 4 linflex modules ? 3 dspi modules with automatic chip select generation ? 4 flexcan interfaces (2.0b ac tive) with 32 message objects ? flexray module (v2.1) with dual channel, up to 128 message objects and up to 10 mbit/s ? fast ethernet controller (fec) ?3 i 2 c modules ? four 12-bit analog-to-digital converters (adcs) ? 22 input channels ? programmable cross triggering unit (ctu) to synchronize adc conversion with timer and pwm ? external bus interface ? 16-bit external ddr memory controller ? parallel digital interface (pdi)
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 7 ? on-chip can/uart bootstrap loader ? capable of operating on a single 3.3 v voltage supply ? 3.3 v-only modules: i/o, oscillators, flash memory ? 3.3 v or 5 v modules: adcs, supply to internal vreg ? 1.8?3.3 v supply range: dram/pdi ? operating junction temperature range ?40 to 150 c 1.6 feature details 1.6.1 high-performance e200z7d core processor ? dual 32-bit power architecture ? processor core ? loose or tight core coupling ? freescale variable length enc oding (vle) enhancements for code size footprint reduction ? thirty-two 64-bit general-purpose registers (gprs) ? memory management unit (mmu) with 64-entry fully-a ssociative translation look-aside buffer (tlb) ? branch processing unit ? fully pipelined load/store unit ? 16 kb instruction and 16 kb data cach es per core with line locking ? four way set associative ? two 32-bit fetches per clock ? eight-entry store buffer ? way locking ? supports tag and data cache parity ? supports edc for instruction cache ? vectored interrupt support ? signal processing engine 2 (spe2) auxiliary processing unit (apu) operating on 64-bit general purpose registers ? floating point ? ieee ? 754 compatible with software wrapper ? single precision in hardware; double precision with software library ? conversion instructions between single precision floating point and fixed point ? long cycle time instructions (except for guarded load s) do not increase interrupt latency in the MPC5675K ? to reduce latency, long cycle time instructions are aborted upon interrupt requests ? extensive system development support through nexus debug module 1.6.2 crossbar switch (xbar) ? 32-bit address bus, 64-bit data bus ? simultaneous accesses from different mast ers to different slaves (there is no clock penalty when a parked master accesses a slave) 1.6.3 memory protection unit (mpu) each master (edma, flexray, cpu) can be assigned different access rights to each region.
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 8 ? 16-region mpu with concurrent checks against each master access ? 32-byte granularity for protected address region 1.6.4 enhanced direct memory access (edma) controller ? 32 channels support independent 8-, 16-, 32-bit single value or block transfers ? supports variable-sized queues and circular queues ? source and destination addr ess registers are independently configured to post-increment or remain constant ? each transfer is initiated by a peri pheral, cpu, or edma channel request ? each edma channel can optionally send an interrupt requ est to the cpu on completion of a single value or block transfer 1.6.5 interrupt controller (intc) ? 208 peripheral interrupt requests ? 8 software settable sources ? unique 9-bit vector per interrupt source ? 16 priority levels with fixed ha rdware arbitratio n within priority levels for each interrupt source ? priority elevation for shared resources 1.6.6 frequency-modulated phase-locked loop (fmpll) two fmplls are available on each device. each fmpll allows the user to generate high speed system clocks starting from a minimum reference of 4 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the pll multiplication factor and output clock divider ratio are software configurable . the fmplls have the following major features: ? input frequency: 4?40 mhz continuous range (limited by the crystal oscillator) ? voltage controlled oscillator (vco) range: 256?512 mhz ? frequency modulation via software control to reduce and control emission peaks ? modulation depth 2% if centered or 0% to ?4% if downshifted via software control register ? modulation frequency: triangular modulation with 25 khz nominal rate ? option to switch m odulation on and off via software interface ? reduced frequency divider (rfd) for reduced frequency operation without re-lock ? 2 modes of operation ? normal pll mode with crystal reference (default) ? normal pll mode with external reference ? lock monitor circuitry with lock status ? loss-of-lock detection for reference and feedback clocks ? self-clocked mode (scm) operation ? auxiliary fmpll ? used for flexray due to precise symbol rate requirement by the protocol ? used for motor control periphery and connected ip (a/d digital interface ct u) to allow independent frequencies of operation for pwm and timers as well as jitter-free control ? option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop ? allows running motor control periphery at different (precisely lower, equal, or higher, as required) frequency than the system to ensure higher resolution
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 9 1.6.7 external bus interface (ebi) ? available on 473-pin devices ? data and address options: ? 16-bit data and a ddress (non-muxed) ? 32-bit data and address (bus-muxed) ? mpc5561 324 bga compatibility mode: 16-bit data bus, 24-bi t address bus is default addr[8:31], but configurable to 26-bit address bus ? memory controller with support for various memory types ? non-burst and burst mode sdr flash and sram ? asynchronous/legacy flash and sram ? configurable bus speed modes ? support for 2 mb address space ? chip select and write/byte enable optio ns as presented in the pin-muxing tabl e in the ?signal description? chapter of ? the MPC5675K reference manual ? configurable wait states (via chip selects) ? optional automatic clkout gating to save power and reduce emi 1.6.8 on-chip flash memory ? up to 2 mb code flash memory with ecc ? 64 kb data flash memory with ecc ? censorship protection scheme to prevent flash content visibility ? multiple block sizes to support features such as boot block, operating system block, and eeprom emulation ? read-while-write with multiple partitions ? parallel programming mode to s upport rapid end-of-line programming ? hardware programming state machine 1.6.9 cache memory ? harvard architecture cache ? 16 kb instruction / 16 kb data ? four-way set-associative harvard (i nstruction and data) 256-bit long cache ? two 32-bit fetches per clock ? eight-entry store buffer ? way locking ? supports tag and data cache parity ? supports edc for instruction cache 1.6.10 on-chip internal static ram (sram) ? up to 512 kb general-purpose sram ? ecc performs single-bit correction, double-bit error detection ? address included in ecc checkbase
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 10 1.6.11 dram controller the dram controller (available only on 473-pin devices) is a mu lti-port controller that monitors incoming requests on the three ahb slave ports and decides (at each rising clock edge) what command needs to be se nt to the external dram. the dram controller on this device supports the following types of memories: ? mobile ddr (mddr) ? ddr 1 ? ddr 2 (optional) ?sdr the controller has th e following features: ? optimized timing for 32-b yte bursts and single read accesses on the ahb interface ? optimized timing for 8-byte and 16-byte bursts on the dramc interface ? supports priority el evation on the slave po rts for single accesses ? 16-bit wide dram interface ? one chip select (cs) ? mddr memory controller ? 16-bit external interface ? address range up to 8 mb 1.6.12 boot assist module (bam) ? enables booting via serial mode (flexcan, linflex) ? handles static mode in case of an erroneous boot procedure ? implemented in 8 kb rom ? supports lock step mode (lsm) an d decoupled parallel mode (dpm) 1.6.13 parallel data interface (pdi) ? support for external ad c and cmos image sensors ? parallel interface operation up to mcu system bus frequency ? selectable data capture from rising or falling edge ? receive fifo with adjust able trigger thresholds ? data width for 8, 10, 12, 14, and 16 bits ? data packing unit to pack input data on 64-bit words ? data packed on 8- or 16- bit boundary, depending on input data width ? binary increasing channel select that allows as many as eight channels to be selected ? frame synchronization through vsync, hsync, pixclk 1.6.14 deserial serial peripher al interface (dspi) modules ? three serial peripheral interfaces ? full duplex communication ports with interrupt and edma request support ? support for all functional modes from qs pi submodule of qsmcm (mpc5xx family) ? support for queues in ram ? six chip selects, expandable to 64 with external demultiplexers ? programmable frame size, baud rate, clock delay, and clock phase on a per-frame basis
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 11 ? modified spi mode for interfacing to periph erals with longer setup time requirements ? support for up to 60 mbit/s in slave only rx mode 1.6.15 serial communication interface module (linflex) the linflex on this device features the following: ? supports lin master mode, lin slave mode, and uart mode ? lin state machine compliant to lin1.3, 2.0, and 2.1 specifications ? manages lin frame transmission an d reception without cpu intervention ? lin features ? autonomous lin frame handling ? message buffer to store as many as 8 data bytes ? supports messages as long as 64 bytes ? detection and flagging of lin errors (sync field, delimiter, id parity, b it framing, checksum and timeout errors) ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features (loop back, lin bus stuck dominant detection) ? interrupt-driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? uart mode ? full-duplex operation ? standard non return-to-ze ro (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit, 9-bit, or 16-bit words) ? configurable parity scheme: none, odd, even, always 0 ? speed as fast as 2 mbit/s ? error detection and flagging (parity, noise, and framing errors) ? interrupt-driven operation with four interrupt sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate m odulus counter and 16-bit fractional ? two receiver wake-up methods ? support for dma-enabled transfers 1.6.16 flexcan ? thirty-two message buffers each ? full implementation of the can protocol specification, version 2.0b ? programmable acceptance filters ? individual rx filtering per message buffer ? short latency time for high priority transmit messages ? arbitration scheme according to me ssage id or message buffer number ? listen-only mode capabilities ? programmable clock source: syst em clock or oscillator clock
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 12 ? reception queue possible by setting more than one rx message buffer with the same id ? backwards compatible with previous flexcan modules ? safety can features on 1 can mo dule as implemented on mpc5604p 1.6.17 dual-channel flexray controller ? full implementation of flexray protocol specification 2.1 ? sixty-four configurable message buffers can be handled ? message buffers configurab le as tx, rx, or rxfifo ? message buffer size configurable ? message filtering for all message buffers ba sed on frameid, cycle count, and message id ? programmable acceptance filter s for rxfifo message buffers ? dual channel, each at up to 10 mbit/s data rate 1.6.18 periodic interrupt timer (pit) the pit module implements the features below: ? four general-purpose interrupt timers ? 32-bit counter resolution ? clocked by system clock frequency ? 32-bit counter for real time interrupt, clocked from main external oscillator ? can be used for software tick or dma trigger operation 1.6.19 system timer module (stm) the stm implements the features below: ? replicated periphery to provide safety m easures respective to high safety integrity levels (for example, sil 3, asil d) ? up-counter with four output compare registers ? os task protection and hardware tick implementation as per current state-of-the -art autosar requirement 1.6.20 motor control (motc) peripherals the peripherals in this section can be used for general-purpos e applications, but are specifica lly designed for motor control (motc) applications. 1.6.20.1 flexpwm the pulse width modulator module (flexpwm) contains three pwm channels, each of which is co nfigured to control a single half-bridge power stage. there may al so be one or more fault channels. this pwm is capable of controlling most motor types: ac induction motors (acim), permanent magnet ac motors (pmac), both brushless (bldc) and brush dc motors (bdc), switched (srm) and variable reluctance motors (vrm), and stepper motors. a flexpwm module implements the following features: ? 16 bits of resolution for center, ed ge aligned, and asymmetrical pwms ? maximum operating frequency lower than or equal to platform frequency ? clock source not modulated and independent from system clock (generated via auxiliary pll) ? fine granularity control for enhanced resolution of the pwm period
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 13 ? pwm outputs can operate as complementary pairs or independent channels ? ability to accept signed nu mbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hardware or other pwm is supported ? double-buffered pwm registers ? integral reload rates from 1 to 16 ? half-cycle reload capability ? multiple adc trigger events can be generated per pwm cycle via hardware ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and bottom deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software control for each pwm output ? all outputs can be forced to a value simultaneously ? pwmx pin can optionally output a third signal from each channel ? channels not used for pwm generation can be used for: ? buffered output compare functions ? input capture functions ? enhanced dual-edge capture functionality ? option to supply the source for each complementar y pwm signal pair from any of the following: ? external digital pin ? internal timer channel ? external adc input, taking into account valu es set in adc high and low limit registers ? supports safety measures using dma 1.6.20.2 cross triggering unit (ctu) the ctu provides automatic generation of adc conversion requests on user-selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration. the ctu implements the following features: ? cross triggering between adc, fl expwm, etimer, and external pins ? double-buffered trigger generation unit with as many as eight independent triggers generated from external triggers ? maximum operating frequency lower than or equal to platform ? trigger generation unit configurable in sequential mode or in triggered mode ? trigger delay unit to compensate the delay of external low-pass filter ? double-buffered global trigger unit allowing etim er synchronization and/or adc command generation ? double-buffered adc command list pointers to minimize adc trigger unit update ? double-buffered adc conversion command list with as many as twenty-four adc commands ? each trigger has the capability to generate consecutive commands ? adc conversion command allows controlling adc channe l from each adc, single or synchronous sampling, independent result queue selection ? dma support with safety features
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 14 1.6.20.3 analog-to-digital converter (adc) ? four independent adcs with 12-bit a/d resolution ? common mode conversion range of 0?5 v or 0?3.3 v ? twenty-two single-ended input channels ? supports eight fifo queues with fixed priority ? queue modes with priority-based preemption; initiated by software command, inte rnal, or external triggers ? dma and interrupt request support 1.6.20.4 etimer module three 16-bit general purpose up/down timer/counters per module are implemented with the following features: ? ability to operate up to platform frequency ? individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) ? maximum count rate ? equals peripheral clock/2 for external event counting ? equals peripheral clock for internal clock counting ? cascadeable counters ? programmable count modulo ? quadrature decode capabilities ? counters can share available input pins ? count once or repeatedly ? preloadable counters ? pins available as gpio when timer functionality is not in use ? dma support 1.6.21 redundancy control and checker unit (rccu) the rccu checks all outputs of the sphere of replication (addre sses, data, control signals). it has the following features: ? duplicated module to enable high di agnostic coverage (check of checker) ? replicated ip to be used as check ers on the pbridge output, flash controller output, sram output, dma channel mux inputs 1.6.22 software watchdog timer (swt) this module implements the features below: ? replicated periphery to provide safety m easures respective to high safety integrity levels (for example, sil 3, asil d) ? fault-tolerant output ? safe internal rc oscillator as reference clock ? windowed watchdog
introduction MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 15 ? program flow control monitor with 16-bit pseudorandom key generation ? provides measures to target high safety inte grity levels (for example, sil 3, asil d) 1.6.23 fault collection and control unit (fccu) the fccu module has the following features: ? redundant collection of hardware checker results ? redundant collection of error information and la tch of faults from critical modules on the device ? collection of test results ? configurable and graded fault control ? internal reactions (no in ternal reaction, nmi, reset, or safe mode) ? external reaction (failure is reported to the outside world via configurable output pins) 1.6.24 system integration unit lite (siul) the siul controls mcu reset configurati on, pad configuration, external interr upt, general purpose i/o (gpio), internal peripheral multiplexing, and the system reset operation. the reset configuration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the siul provides th e following features: ? centralized pad control on a per-pin basis ? pin function selection ? configurable weak pullup/pulldown ? configurable slew rate control (slow/medium/fast) ? hysteresis on gpio pins ? configurable automatic safe mode pad control ? input filtering for external interrupts 1.6.25 cyclic redundancy checker (crc) unit the crc module is a configurable multiple data flow unit to compute crc signatures on data written to an input register. the crc unit has the following features: ? three sets of registers to allow thr ee concurrent contexts with possibly different crc computations, each with a selectable polynomial and seed ? computes 16- or 32-bit wide crc on the fly (single-cycle computati on) and stores the result in an internal register ? implements the followi ng standard crc polynomials: ? x 16 + x 12 + x 5 + 1 [16-bit crc-ccitt] ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 [32-bit crc-ethernet(32)] ? key engine to be coupled with comm unication periphery where crc application is added to allow implementation of safe communication protocol ? offloads the core from cycl e-consuming crc and helps in checking the conf iguration signature for safe start-up or periodic procedures ? connected as a peripheral on the internal peripheral bus ? provides dma support
MPC5675K microcontroller data sheet, rev. 7 introduction freescale semiconductor 16 1.6.26 non-maskable interrupt (nmi) the non-maskable interrupt with de-glitching filter is available to support high priority core exceptions. 1.6.27 system status and configuration module (sscm) the sscm on the MPC5675K features the following: ? system configuration and status ? debug port status and debug port enable ? multiple boot code starting locations out of reset throu gh implementation of search for valid reset configuration halfword ? sets up the mmu to allow user boot code to execute as eith er classic power architecture book e code (default) or as freescale vle code out of flash ? supports serial bootloading of either classic power architecture book e code (d efault) or freescale vle code ? detection of user boot code ? automatic switch to serial boot mode if internal flash is blank or invalid 1.6.28 nexus development interface (ndi) ? per ieee-isto 5001-2008 ? real-time development support for power architecture core through nexus class 3 (some class 4 support) ? nexus support to snoop system sram traffic ? data trace of flexray accesses ? read and write access ? configured via the ieee 1149.1 (jtag) port ? high bandwidth mode for fast message transmission ? reduced bandwidth mode for reduced pin usage 1.6.29 ieee 1149.1 jtag controller (jtagc) ? ieee 1149.1-2001 test acce ss port (tap) interface ? jcomp input that provides the ability to share the tap ?selectable modes of operation include jtagc/debug or normal system operation ? 5-bit instruction register that supports ieee 1149.1-2001 defined instructions ? 5-bit instruction register that supports additional public instructions ? three test data registers: ? bypass register ? boundary scan register ? device identification register ? tap controller state machine that cont rols the operation of the data register s, instruction register, and associated circuitry
package pinouts and signal descriptions MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 17 2 package pinouts and signal descriptions 2.1 package pinouts figure 2 shows the MPC5675K in the 257 mapbga package. figure 3 , figure 4 , figure 5 , and figure 6 show the MPC5675K in the 473 mapbga package. figure 2. MPC5675K 257 mapbga pinout (top view) 1234567891011121314151617 a vss_ hv_io vss_ hv_io vdd_ hv_io nexus mdo[5] nexus mdo[7] nexus mdo[9] flexray cb_tx flexray ca_tr_ en vdd_ hv_io fec rxd[2] fec rx_ clk fec rxd[0] fec mdio fec tx_en fec txd[3] vss_ hv_io vss_ hv_io a b vss_ hv_io vss_ hv_io mc_cgl clk_out can1 txd nexus mdo [14] dspi2 cs1 flexray cb_tr_ en flexray ca_tx vss_ hv_io fec rxd[3] fec rx_er fec rxd[1] fec tx_er fec tx_ clk can0 txd vdd_ hv_io vss_ hv_io b c vdd_ hv_io nexus mdo [15] vss_ hv_io fccu_ f[1] flexray cb_rx etimer0 etc[0] etimer0 etc[1] etimer0 etc[2] etimer0 etc[3] jcomp fec crs fec txd[0] fec col can0 rxd vss_ hv_pdi pdi data [5] pdi clock c d nexus mdo [2] nexus mdo [3] can1 rxd dspi0 sout reserv ed etimer0 etc[5] etimer0 etc[4] vdd_ hv_fla vss_ hv_fla fec txd[2] fec txd[1] fec rx_dv fec mdc vdd_ hv_pdi vss_ hv_io pdi data [0] pdi data [1] d e nexus mdo [0] nexus mdo [1] flexray ca_rx nmi pdi line_v pdi data [2] pdi data [3] pdi data [4] e f nexus mdo[6] nexus mdo [11] dspi1 sout dspi1 sin vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor mc_cgl clk_out pdi data [6] pdi data [7] pdi data [8] f g nexus mdo [4] vdd_ hv_io dspi0 sck dspi1 sck vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor pdi data [9] pdi data [10] pdi data [11] pdi frame_ v g h nexus mdo [10] vss_ hv_io dspi0 cs0 dspi1 cs0 vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor pdi data [12] pdi data [13] vdd_ hv_ pdi flexpwm 0 x[0] h j nexus mcko nexus mdo[8] dspi2 cs0 dspi2 cs2 vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor pdi data [14] pdi data [15] vss_ hv_ pdi flexpwm 0 x[1] j k nexus mseo_ b[0] nexus mseo_ b[1] nexus rdy_b dspi0 sin vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor flexpwm 0 x[2] flexpwm 0 x[3] flexpwm 0 a[1] flexpwm 0 b[0] k l nexus evto_b nexus evti_b dspi2 sck nexus mdo [13] vdd_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vss_ lv _ cor vdd_ lv _ cor vdd_hv _dram_ vref tck flexpwm 0 b[1] tdo l m vdd_ hv_ osc vdd_ hv_io dspi1 cs2 nexus mdo [12] vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor vdd_ lv _ cor flexpwm 0 b[2] tdi tms flexpwm 1 a[1] m n xtalin vss_ hv_io dspi0 cs3 vss_ lv _ p l l flexpwm 0 b[3] flexpwm 0 a[2] flexpwm 1 a[0] flexpwm 1 b[0] n p vss_ hv_ osc reset dspi0 cs2 vdd_ lv _ p l l etimer1 etc[1] etimer1 etc[2] adc0 an[0] etimer1 etc[3] vss_ hv_io vdd_ hv_io adc0_ adc1 an[14] etimer1 etc[4] etimer1 etc[5] vdd_ hv_io flexpwm 0 a[3] flexpwm 0 a[0] flexpwm 1 b[1] p r xtal out fccu_ f[0] vss_hv _io dspi1 cs3 adc2 an[0] adc2 an[3] vdd_ hv_ adr_13 adc2_ adc3 an[14] vdd_ hv_ adr_02 adc0 an[2] adc0_ adc1 an[13] adc1 an[1] vreg_c trl lin0 txd vss_ hv_io flexpwm 1 a[2] flexpwm 1 b[2] r t vss_ hv_io vdd_ hv_io dspi2 sout adc3 an[0] adc3 an[3] adc2 an[2] vss_ hv_ adr_13 adc2_ adc3 an[13] vss_ hv_ adr_02 adc0 an[1] adc0_ adc1 an[12] adc1 an[0] adc1 an[2] lin0 rxd etimer1 etc[0] vdd_ hv_io vss_ hv_io t u vss_ hv_io vss_ hv_io dspi2 sin adc3 an[1] adc3 an[2] adc2 an[1] adc2_ adc3 an[11] adc2_ adc3 an[12] vdd_ hv_ adv vss_ hv_ adv adc0_ adc1 an[11] vreg_ int_en able reset_ sup vdd_hv _pmu vss_ hv_ pmu vss_ hv_io vss_ hv_io u 1234567891011121314151617
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 18 figure 3. MPC5675K 473 mapbga pinout (northwest, viewed from above) 123456789101112 a vss_ hv_io vss_ hv_io vdd_ hv_io nexus mdo[5] nexus mdo[7] nexus mdo[9] flexray cb_tx flexray ca_tr_en fec rx_dv fec mdio fec tx_clk fec tx_en b vss_ hv_io vss_ hv_io mc_cgl clk_out can1 txd nexus mdo[14] dspi2 cs1 flexray cb_tr_en flexray ca_tx fec rxd[3] fec rx_er fec txd[0] fec rxd[0] c vdd_ hv_io nexus mdo[15] vss_ hv_io fccu_ f[1] flexray cb_rx etimer0 etc[4] etimer0 etc[1] etimer0 etc[2] etimer0 etc[3] fec txd[2] fec txd[1] fec crs d nexus mdo[1] nexus mdo[3] can1 rxd dspi0 sout reserved etimer0 etc[5] etimer0 etc[0] vdd_ hv_io vss_ hv_io jcomp vss_ hv_io vss_ hv_fla e nexus mdo[0] nexus mdo[2] flexray ca_rx nmi f nexus mdo[10] nexus mdo[11] nexus mdo[6] nexus mdo[4] vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_c o r vdd_ lv_c o r vdd_ lv_ c or vdd_ lv_ c or g nexus mcko vdd_ hv_io nexus mdo[8] nexus mseo_b[1] vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or h nexus evto_b vss_ hv_io nexus mseo_b[0] nexus evti_b vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or j nexus rdy_b nexus mdo[13] nexus mdo[12] dspi1 sin vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or k dspi0 sck dspi1 cs0 dspi1 sck dspi1 sout vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or l dspi0 cs0 dspi2 cs2 dspi2 cs0 vss_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or m flexpwm0 x[0] vdd_ hv_io dspi0 sin vdd_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_c o r vss_ lv_c o r vss_ lv_ c or vss_ lv_ c or
package pinouts and signal descriptions MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 19 figure 4. MPC5675K 473 mapbga pinout (southwest, viewed from above) figure 5. MPC5675K 473 mapbga pinout (northeast, viewed from above) n flexpwm0 a[0] vss_ hv_io flexpwm0 x[1] flexpwm0 b[2] vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or p flexpwm0 b[0] flexpwm0 b[1] flexpwm0 a[2] flexpwm0 a[3] vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or r flexpwm0 x[2] flexpwm0 x[3] flexpwm0 a[1] vss_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or t flexpwm0 b[3] flexpwm1 a[0] flexpwm1 a[1] vdd_ hv_io vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or u flexpwm1 b[0] flexpwm1 b[1] flexpwm1 a[2] dspi2 sck vdd_ lv _ c o r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or vss_ lv_ c or v vdd_ hv_osc vdd_ hv_io flexpwm1 b[2] dspi1 cs2 vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_ c or vdd_ lv_ c or vdd_ lv_ c or vdd_ lv_ c or w xtalin vss_ hv_io dspi0 cs3 vss_ lv_pll y vss_ hv_osc reset dspi0 cs2 vdd_ lv_pll flexpwm1 x[0] adc3 an[0] adc2_adc3 an[11] adc2_adc3 an[14] etimer1 etc[1] etimer1 etc[2] etimer1 etc[3] vss_ hv_io aa xtalout fccu_ f[0] vss_ hv_io dspi1 cs3 flexpwm1 x[1] adc3 an[1] adc2_adc3 an[12] adc2 an[0] vdd_ hv_adv vss_ hv_adv adc0 an[2] adc0 an[5] ab vss_ hv_io vdd_ hv_io dspi2 sout flexpwm1 x[2] flexpwm1 x[3] adc3 an[2] adc2_adc3 an[13] adc2 an[1] adc2 an[2] adc0 an[0] adc0 an[4] adc0 an[6] ac vss_ hv_io vss_ hv_io dspi2 sin flexpwm1 a[3] flexpwm1 b[3] adc3 an[3] vdd_hv_ adr_23 vss_hv_ adr_23 adc2 an[3] adc0 an[1] adc0 an[3] vdd_ hv_adr_0 123456789101112 13 14 15 16 17 18 19 20 21 22 23 fec txd[3] vdd_ hv_io pdi data[3] pdi data[1] pdi clock pdi data[7] pdi data[10] pdi data[13] pdi data[15] vss_ hv_io vss_ hv_io a fec tx_er vss_ hv_io pdi data[6] pdi data[4] pdi data[0] pdi line_v pdi data[9] pdi data[14] can0 txd vdd_ hv_io vss_ hv_io b fec rx_clk fec rxd[1] fec col pdi data[5] pdi data[2] pdi data[8] pdi data[12] can0 rxd vss_ hv_pdi siul gpio[197] dramc cas c vdd_ hv_fla fec rxd[2] fec mdc vdd_ hv_pdi vss_ hv_pdi pdi data[11] pdi frame_v vdd_ hv_pdi dramc ba[1] siul gpio[195] dramc ba[0] d mc_cgl clk_out siul gpio[149] dramc cs0 dramc ba[2] e vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_ c or vdd_ lv_ c or vdd_ lv _ c o r vdd_ lv _ c o r dramc ras siul gpio[194] siul gpio[148] dramc d[5] f vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r siul gpio[196] dramc dqs[0] dramc dm[0] dramc d[7] g vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc d[2] vdd_hv_ dram_vtt vdd_hv_ dram vss_hv_ dram h vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc d[0] dramc d[1] dramc d[3] dramc d[6] j vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r vss_ hv_io dramc d[4] dramc d[8] dramc d[9] k vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r vdd_ hv_io vdd_hv_ dram_vtt vss_hv_ dram vdd_hv_ dram l vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc odt dramc web dramc d[11] dramc d[10] m
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 20 figure 6. MPC5675K 473 mapbga pinout (southeast, viewed from above) 2.2 pin descriptions the following sections provide signal descriptions and relate d information about the functionality and configuration for this device. 2.2.1 pad types table 2 lists the pad types used on the MPC5675K. vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc dqs[1] dramc dm[1] dramc d[13] dramc d[12] n vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc d[14] dramc d[15] vss_hv_ dram vdd_hv_ dram p vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r vdd_hv_ dram_vref dramc add[3] dramc cke dramc clkb r vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc add[8] dramc add[9] dramc add[1] dramc clk t vss_ lv _ c o r vss_ lv _ c o r vss_ lv_ c or vss_ lv_ c or vss_ lv _ c o r vdd_ lv _ c o r dramc add[6] dramc add[12] vdd_hv_ dram dramc add[0] u vdd_ lv _ c o r vdd_ lv _ c o r vdd_ lv_ c or vdd_ lv_ c or vdd_ lv _ c o r vdd_ lv _ c o r lin0 txd dramc add[13] vss_hv_ dram dramc add[2] v lin0 rxd dramc add[14] dramc add[7] dramc add[4] w vdd_ hv_io adc0_adc1 an[11] etimer1 etc[5] etimer1 etc[4] adc1 an[8] adc1 an[6] tck vdd_hv_io dramc add[15] dramc add[11] dramc add[5] y adc0 an[8] adc0_adc1 an[12] adc1 an[0] adc1 an[2] adc1 an[5] adc1 an[7] tdi etimer1 etc[0] vss_hv_io lin1 txd dramc add[10] aa adc0 an[7] adc0_adc1 an[13] adc1 an[1] adc1 an[3] adc1 an[4] tdo tms reserved lin1 rxd vdd_ hv_io vss_ hv_io ab vss_ hv_adr_0 adc0_adc1 an[14] vdd_ hv_adr_1 vss_ hv_adr_1 vdd_ hv_pmu vreg_ctrl vss_ hv_pmu reset_ sup vreg_int_ enable vss_ hv_io vss_ hv_io ac 13 14 15 16 17 18 19 20 21 22 23 table2. pad types pad type description gp slow slow buffer with cmos sc hmitt trigger and pullup/pulldown. gp slow/fast programmable slow/fast buffer with cmos schmitt trigger, pullup/pulldown. gp slow/medium programmable slow/medium buffer with cmos schmitt trigger, pullup/pulldown. programmable slow/medium buffer with cmos schmitt trigger, pullup/pulldown and injection proof analog switch. gp slow/symmetric programmable slow/symmetric buffer with cmos schmitt trigger, pullup/pulldown. pdi medium medium slew-rate output with four sele ctable slew rates. contains an input buffer and weak pullup/pulldown. pdi fast fast slew-rate output with four selectable slew rates. contains an input buffer and weak pullup/pulldown.
package pinouts and signal descriptions MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 21 2.2.2 power supply and reference voltage pins table 3 shows the supply pins for the mp c5675k in the 257 m apbga package. table 5 shows the supply pins for the MPC5675K in the 473 mapbga package. table 4 and table 6 show the pins not populated on the MPC5675K 257 mapbga and 473 mapbga packages, respectively. dram acc bidirectional ddr pad. can be conf igured to support lpddr half strength, lpddr full strength, ddr1, ddr2 half st rength, ddr2 full st rength, and sdr. dram clk differential clock driver. dram dq bidirectional ddr pad with integrated odt. can be configured to support lpddr half strength, lpddr full strength, ddr1, ddr2 half strength, ddr2 full strength, and sdr. dram odt ctl enable on die termination control. analog cmos schmitt trigger cell with injection proof analog switch. analog shared cmos schmitt trigger cell with two injection-proof analog switches. table 3. 257 mapbga supply pins ball number ball name pad type ball number ball name pad type v dd a3 vdd_hv_io vdd_hv f9 vdd_lv_cor vdd_lv a9 vdd_hv_io vdd_hv f10 vdd_lv_cor vdd_lv b16 vdd_hv_io vdd_hv f11 vdd_lv_cor vdd_lv c1 vdd_hv_io vdd_hv f12 vdd_lv_cor vdd_lv g2 vdd_hv_io vdd_hv g6 vdd_lv_cor vdd_lv m2 vdd_hv_io vdd_hv g12 vdd_lv_cor vdd_lv p10 vdd_hv_io vdd_hv h6 vdd_lv_cor vdd_lv p14 vdd_hv_io vdd_hv h12 vdd_lv_cor vdd_lv t2 vdd_hv_io vdd_hv j6 vdd_lv_cor vdd_lv t16 vdd_hv_io vdd_hv j12 vdd_lv_cor vdd_lv l14 vdd_hv_dram_vref vdd_hv k6 vdd_lv_cor vdd_lv d8 vdd_hv_fla vdd_hv k12 vdd_lv_cor vdd_lv m1 vdd_hv_osc vdd_hv l6 vdd_lv_cor vdd_lv d14 vdd_hv_pdi vdd_hv l12 vdd_lv_cor vdd_lv h16 vdd_hv_pdi vdd_hv m6 vdd_lv_cor vdd_lv u14 vdd_hv_pmu vdd_hv m7 vdd_lv_cor vdd_lv r7 vdd_hv_adr_13 vdd_hv_a m8 vdd_lv_cor vdd_lv table 2. pad types (continued) pad type description
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 22 r9 vdd_hv_adr_02 vdd_hv_a m9 vdd_lv_cor vdd_lv u9 vdd_hv_adv vdd_hv_a m10 vdd_lv_cor vdd_lv f6 vdd_lv_cor vdd_lv m11 vdd_lv_cor vdd_lv f7 vdd_lv_cor vdd_lv m12 vdd_lv_cor vdd_lv f8 vdd_lv_cor vdd_lv p4 vdd_lv_pll vdd_lv v ss a1 vss_hv_io vss_hv g7 vss_lv_cor vss_lv a2 vss_hv_io vss_hv g8 vss_lv_cor vss_lv a16 vss_hv_io vss_hv g9 vss_lv_cor vss_lv a17 vss_hv_io vss_hv g10 vss_lv_cor vss_lv b1 vss_hv_io vss_hv g11 vss_lv_cor vss_lv b2 vss_hv_io vss_hv h7 vss_lv_cor vss_lv b9 vss_hv_io vss_hv h8 vss_lv_cor vss_lv b17 vss_hv_io vss_hv h9 vss_lv_cor vss_lv c3 vss_hv_io vss_hv h10 vss_lv_cor vss_lv d15 vss_hv_io vss_hv h11 vss_lv_cor vss_lv h2 vss_hv_io vss_hv j7 vss_lv_cor vss_lv n2 vss_hv_io vss_hv j8 vss_lv_cor vss_lv p9 vss_hv_io vss_hv j9 vss_lv_cor vss_lv r3 vss_hv_io vss_hv j10 vss_lv_cor vss_lv r15 vss_hv_io vss_hv j11 vss_lv_cor vss_lv t1 vss_hv_io vss_hv k7 vss_lv_cor vss_lv t17 vss_hv_io vss_hv k8 vss_lv_cor vss_lv u1 vss_hv_io vss_hv k9 vss_lv_cor vss_lv u2 vss_hv_io vss_hv k10 vss_lv_cor vss_lv u16 vss_hv_io vss_hv k11 vss_lv_cor vss_lv u17 vss_hv_io vss_hv l7 vss_lv_cor vss_lv d9 vss_hv_fla vss_hv l8 vss_lv_cor vss_lv p1 vss_hv_osc vss_hv l9 vss_lv_cor vss_lv c15 vss_hv_pdi vss_hv l10 vss_lv_cor vss_lv j16 vss_hv_pdi vss_hv l11 vss_lv_cor vss_lv t9 vss_hv_adr_02 vss_hv_a n4 vss_lv_pll vss_lv t7 vss_hv_adr_13 vss_hv_a u15 vss_hv_pmu vss_lv u10 vss_hv_adv vss_hv_a table 3. 257 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
package pinouts and signal descriptions MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 23 table4. 257mapbga pins not populated on package e5 e6 e7 e8 e9 e10 e11 e12 e13 f5 f13 g5 g13 h5 h13 j5 j13 k5 k13 l5 l13 m5 m13 n5 n6 n7 n8 n9 n10 n11 n12 n13 table 5. 473 mapbga supply pins ball number ball name pad type ball number ball name pad type v dd a3 vdd_hv_io vdd_hv f15 vdd_lv_cor vdd_lv a14 vdd_hv_io vdd_hv f16 vdd_lv_cor vdd_lv b22 vdd_hv_io vdd_hv f17 vdd_lv_cor vdd_lv c1 vdd_hv_io vdd_hv f18 vdd_lv_cor vdd_lv d8 vdd_hv_io vdd_hv g6 vdd_lv_cor vdd_lv g2 vdd_hv_io vdd_hv g18 vdd_lv_cor vdd_lv l20 vdd_hv_io vdd_hv h6 vdd_lv_cor vdd_lv m2 vdd_hv_io vdd_hv h18 vdd_lv_cor vdd_lv m4 vdd_hv_io vdd_hv j6 vdd_lv_cor vdd_lv t4 vdd_hv_io vdd_hv j18 vdd_lv_cor vdd_lv v2 vdd_hv_io vdd_hv k6 vdd_lv_cor vdd_lv y13 vdd_hv_io vdd_hv k18 vdd_lv_cor vdd_lv y20 vdd_hv_io vdd_hv l6 vdd_lv_cor vdd_lv ab2 vdd_hv_io vdd_hv l18 vdd_lv_cor vdd_lv ab22 vdd_hv_io vdd_hv m6 vdd_lv_cor vdd_lv ac12 vdd_hv_adr_0 vdd_hv_a m18 vdd_lv_cor vdd_lv ac15 vdd_hv_adr_1 vdd_hv_a n6 vdd_lv_cor vdd_lv ac7 vdd_hv_adr_23 vdd_hv_a n18 vdd_lv_cor vdd_lv aa9 vdd_hv_adv vdd_hv_a p6 vdd_lv_cor vdd_lv h22 vdd_hv_dram vdd_hv p18 vdd_lv_cor vdd_lv l23 vdd_hv_dram vdd_hv r6 vdd_lv_cor vdd_lv p23 vdd_hv_dram vdd_hv r18 vdd_lv_cor vdd_lv u22 vdd_hv_dram vdd_hv t6 vdd_lv_cor vdd_lv r20 vdd_hv_dram_vref vdd_hv t18 vdd_lv_cor vdd_lv h21 vdd_hv_dram_vtt vdd_hv u6 vdd_lv_cor vdd_lv l21 vdd_hv_dram_vtt vdd_hv u18 vdd_lv_cor vdd_lv
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 24 d13 vdd_hv_fla vdd_hv v6 vdd_lv_cor vdd_lv v1 vdd_hv_osc vdd_hv v7 vdd_lv_cor vdd_lv d16 vdd_hv_pdi vdd_hv v8 vdd_lv_cor vdd_lv d20 vdd_hv_pdi vdd_hv v9 vdd_lv_cor vdd_lv ac17 vdd_hv_pmu vdd_hv v10 vdd_lv_cor vdd_lv f6 vdd_lv_cor vdd_lv v11 vdd_lv_cor vdd_lv f7 vdd_lv_cor vdd_lv v12 vdd_lv_cor vdd_lv f8 vdd_lv_cor vdd_lv v13 vdd_lv_cor vdd_lv f9 vdd_lv_cor vdd_lv v14 vdd_lv_cor vdd_lv f10 vdd_lv_cor vdd_lv v15 vdd_lv_cor vdd_lv f11 vdd_lv_cor vdd_lv v16 vdd_lv_cor vdd_lv f12 vdd_lv_cor vdd_lv v17 vdd_lv_cor vdd_lv f13 vdd_lv_cor vdd_lv v18 vdd_lv_cor vdd_lv f14 vdd_lv_cor vdd_lv y4 vdd_lv_pll vdd_lv v ss a2 vss_hv_io vss_hv l7 vss_lv_cor vss_lv a22 vss_hv_io vss_hv l8 vss_lv_cor vss_lv a23 vss_hv_io vss_hv l9 vss_lv_cor vss_lv b1 vss_hv_io vss_hv l10 vss_lv_cor vss_lv b2 vss_hv_io vss_hv l11 vss_lv_cor vss_lv b14 vss_hv_io vss_hv l12 vss_lv_cor vss_lv b23 vss_hv_io vss_hv l13 vss_lv_cor vss_lv c3 vss_hv_io vss_hv l14 vss_lv_cor vss_lv d9 vss_hv_io vss_hv l15 vss_lv_cor vss_lv d11 vss_hv_io vss_hv l16 vss_lv_cor vss_lv h2 vss_hv_io vss_hv l17 vss_lv_cor vss_lv k20 vss_hv_io vss_hv m7 vss_lv_cor vss_lv l4 vss_hv_io vss_hv m8 vss_lv_cor vss_lv n2 vss_hv_io vss_hv m9 vss_lv_cor vss_lv a1 vss_hv_io vss_hv m10 vss_lv_cor vss_lv r4 vss_hv_io vss_hv m11 vss_lv_cor vss_lv w2 vss_hv_io vss_hv m12 vss_lv_cor vss_lv y12 vss_hv_io vss_hv m13 vss_lv_cor vss_lv aa3 vss_hv_io vss_hv m14 vss_lv_cor vss_lv table 5. 473 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
package pinouts and signal descriptions MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 25 aa21 vss_hv_io vss_hv m15 vss_lv_cor vss_lv ab1 vss_hv_io vss_hv m16 vss_lv_cor vss_lv ab23 vss_hv_io vss_hv m17 vss_lv_cor vss_lv ac1 vss_hv_io vss_hv n7 vss_lv_cor vss_lv ac2 vss_hv_io vss_hv n8 vss_lv_cor vss_lv ac22 vss_hv_io vss_hv n9 vss_lv_cor vss_lv ac23 vss_hv_io vss_hv n10 vss_lv_cor vss_lv ac13 vss_hv_adr_0 vss_hv_a n11 vss_lv_cor vss_lv ac16 vss_hv_adr_1 vss_hv_a n12 vss_lv_cor vss_lv ac8 vss_hv_adr_23 vss_hv_a n13 vss_lv_cor vss_lv aa10 vss_hv_adv vss_hv_a n14 vss_lv_cor vss_lv h23 vss_hv_dram vss_hv n15 vss_lv_cor vss_lv l22 vss_hv_dram vss_hv n16 vss_lv_cor vss_lv p22 vss_hv_dram vss_hv n17 vss_lv_cor vss_lv v22 vss_hv_dram vss_hv p7 vss_lv_cor vss_lv d12 vss_hv_fla vss_hv p8 vss_lv_cor vss_lv y1 vss_hv_osc vss_hv p9 vss_lv_cor vss_lv c21 vss_hv_pdi vss_hv p10 vss_lv_cor vss_lv d17 vss_hv_pdi vss_hv p11 vss_lv_cor vss_lv g7 vss_lv_cor vss_lv p12 vss_lv_cor vss_lv g8 vss_lv_cor vss_lv p13 vss_lv_cor vss_lv g9 vss_lv_cor vss_lv p14 vss_lv_cor vss_lv g10 vss_lv_cor vss_lv p15 vss_lv_cor vss_lv g11 vss_lv_cor vss_lv p16 vss_lv_cor vss_lv g12 vss_lv_cor vss_lv p17 vss_lv_cor vss_lv g13 vss_lv_cor vss_lv r7 vss_lv_cor vss_lv g14 vss_lv_cor vss_lv r8 vss_lv_cor vss_lv g15 vss_lv_cor vss_lv r9 vss_lv_cor vss_lv g16 vss_lv_cor vss_lv r10 vss_lv_cor vss_lv g17 vss_lv_cor vss_lv r11 vss_lv_cor vss_lv h7 vss_lv_cor vss_lv r12 vss_lv_cor vss_lv h8 vss_lv_cor vss_lv r13 vss_lv_cor vss_lv h9 vss_lv_cor vss_lv r14 vss_lv_cor vss_lv h10 vss_lv_cor vss_lv r15 vss_lv_cor vss_lv table 5. 473 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 26 h11 vss_lv_cor vss_lv r16 vss_lv_cor vss_lv h12 vss_lv_cor vss_lv r17 vss_lv_cor vss_lv h13 vss_lv_cor vss_lv t7 vss_lv_cor vss_lv h14 vss_lv_cor vss_lv t8 vss_lv_cor vss_lv h15 vss_lv_cor vss_lv t9 vss_lv_cor vss_lv h16 vss_lv_cor vss_lv t10 vss_lv_cor vss_lv h17 vss_lv_cor vss_lv t11 vss_lv_cor vss_lv j7 vss_lv_cor vss_lv t12 vss_lv_cor vss_lv j8 vss_lv_cor vss_lv t13 vss_lv_cor vss_lv j9 vss_lv_cor vss_lv t14 vss_lv_cor vss_lv j10 vss_lv_cor vss_lv t15 vss_lv_cor vss_lv j11 vss_lv_cor vss_lv t16 vss_lv_cor vss_lv j12 vss_lv_cor vss_lv t17 vss_lv_cor vss_lv j13 vss_lv_cor vss_lv u7 vss_lv_cor vss_lv j14 vss_lv_cor vss_lv u8 vss_lv_cor vss_lv j15 vss_lv_cor vss_lv u9 vss_lv_cor vss_lv j16 vss_lv_cor vss_lv u10 vss_lv_cor vss_lv j17 vss_lv_cor vss_lv u11 vss_lv_cor vss_lv k7 vss_lv_cor vss_lv u12 vss_lv_cor vss_lv k8 vss_lv_cor vss_lv u13 vss_lv_cor vss_lv k9 vss_lv_cor vss_lv u14 vss_lv_cor vss_lv k10 vss_lv_cor vss_lv u15 vss_lv_cor vss_lv k11 vss_lv_cor vss_lv u16 vss_lv_cor vss_lv k12 vss_lv_cor vss_lv u17 vss_lv_cor vss_lv k13 vss_lv_cor vss_lv w4 vss_lv_pll vss_lv k14 vss_lv_cor vss_lv ac19 vss_hv_pmu vss_lv k15 vss_lv_cor vss_lv d5 reserved vss_hv k16 vss_lv_cor vss_lv ab20 reserved vss_hv k17 vss_lv_cor vss_lv table 5. 473 mapbga supply pins (continued) ball number ball name pad type ball number ball name pad type
package pinouts and signal descriptions MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 27 2.2.3 system pins table 7 shows the system pins for the mp c5675k in the 257 mapbga package. table 8 shows the system pins for the MPC5675K in the 473 mapbga package. table6. 473mapbga pins not populated on package e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 e19 f5 f19 g5 g19 h5 h19 j5 j19 k5 k19 l5 l19 m5 m19 n5 n19 p5 p19 r5 r19 t5 t19 u5 u19 v5 v19w5w6w7w8w9w10w11 w12w13w14w15w16w17w18w19 table 7. 257 mapbga system pins ball number ball name weak pull during reset safe mode default condition pad type power domain c4 fccu_f[1] disabled not available gp slow/medium vdd_hv_io c10 jcomp pulldown not available gp slow vdd_hv_io e1 nexus mdo[0] 1 1 do not connect pin directly to a power supply or ground. ? not available gp slow/fast vdd_hv_io e4 nmi pullup not available gp slow vdd_hv_io l15 tck pullup not available gp slow vdd_hv_io m16 tms pullup not available gp slow vdd_hv_io n1 xtalin ? not available analog feedthrough vdd_hv_io p2 reset pulldown not available reset vdd_hv_io r1 xtalout ? not available analog feedthrough vdd_hv_io r2 fccu_f[0] disabled not available gp slow/medium vdd_hv_io r13 vreg_ctrl ?? analog feedthrough vdd_reg u12 vreg_int_enable ?? analog feedthrough vdd_hv_io u13 reset_sup pulldown ? analog feedthrough vdd_hv_io table 8. 473 mapbga system pins ball number ball name weak pull during reset safe mode default condition pad type power domain c4 fccu_f[1] disabled not available gp slow/medium vdd_hv_io d10 jcomp pulldown not available gp slow vdd_hv_io
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 28 e1 nexus mdo[0] 1 ? not available gp slow/fast vdd_hv_io e4 nmi pullup not available gp slow vdd_hv_io r23 dramc clkb ? ? dram clk vdd_hv_dram t23 dramc clk disabled ? dram clk vdd_hv_dram w1 xtalin ? not available analog feedthrough vdd_hv_io y2 reset pulldown not available reset vdd_hv_io y19 tck pullup not available gp slow vdd_hv_io aa1 xtalout ? not available analog feedthrough vdd_hv_io aa2 fccu_f[0] disabled not available gp slow/medium vdd_hv_io ab19 tms pullup not available gp slow vdd_hv_io ac18 vreg_ctrl ? ? analog feedthrough vdd_reg ac20 reset_sup pulldown ? analog feedthrough vdd_hv_io ac21 vreg_int_enable ? ? analog feedthrough vdd_hv_io 1 do not connect pin directly to a power supply or ground. table 8. 473 mapbga system pins (continued) ball number ball name weak pull during reset safe mode default condition pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 29 2.2.4 multiplexed pins table 9 shows the pin multiplexing for the MPC5675K in the 257 mapbga package. table 10 shows the pin multiplexing for the MPC5675K in the 473 mapbga package. table 9. 257 mapbga pin multiplexing ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain a4 gpio nexus mdo[5] 1 a0: siul_gpio[114] a1: _ a2: npc_wrapper_mdo[5] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io a5 gpio nexus mdo[7] 1 a0: siul_gpio[112] a1: _ a2: npc_wrapper_mdo[7] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io a6 gpio nexus mdo[9] 1 a0: siul_gpio[110] a1: _ a2: npc_wrapper_mdo[9] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io a7 gpio flexray cb_tx a0: siul_gpio[51] a1: flexray_cb_tx a2: _ a3: _ i: _ i: _ i: _ ?disabledgp slow/ symmetric vdd_hv_io a8 gpio flexray ca_tr_en a0: siul_gpio[47] a1: flexray_ca_tr_en a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: _ ?disabledgp slow/ symmetric vdd_hv_io a10 gpio fec rxd[2] a0: siul_gpio[213] a1: _ a2: _ a3: dspi2_sout i: fec_rxd[2] i: _ i: siul_eirq[21] ?disabledgp slow/ medium vdd_hv_io a11 gpio fec rx_clk a0: siul_gpio[209] a1: flexray_dbg2 a2: etimer2_etc[2] a3: dspi0_cs6 i: fec_rx_clk i: _ i: siul_eirq[25] ?disabledgp slow/ medium vdd_hv_io a12 gpio fec rxd[0] a0: siul_gpio[211] a1: i2c1_clock a2: _ a3: _ i: fec_rxd[0] i: _ i: siul_eirq[27] ?disabledgp slow/ medium vdd_hv_io
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 30 a13 gpio fec mdio a0: siul_gpio[198] a1: fec_mdio a2: _ a3: dspi2_cs0 i: _ i: _ i: siul_eirq[28] ?disabledgp slow/ medium vdd_hv_io a14 gpio fec tx_en a0: siul_gpio[200] a1: fec_tx_en a2: _ a3: lin0_txd i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io a15 gpio fec txd[3] a0: siul_gpio[204] a1: fec_txd[3] a2: _ a3: dspi2_cs2 i: flexpwm1_fault[2] i: _ i: siul_eirq[29] ?disabledgp slow/ medium vdd_hv_io b3 gpio mc_cgl clk_out a0: siul_gpio[22] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: siul_eirq[18] ?disabledgp slow/ fast vdd_hv_io b4 gpio can1 txd a0: siul_gpio[14] a1: can1_txd a2: _ a3: _ i: _ i: _ i: siul_eirq[13] ?disabledgp slow/ medium vdd_hv_io b5 gpio nexus mdo[14] 1 a0: siul_gpio[219] a1: _ a2: npc_wrapper_mdo[14] a3: can3_txd i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io b6 gpio dspi2 cs1 a0: siul_gpio[9] a1: dspi2_cs1 a2: _ a3: _ i: flexpwm0_fault[0] i: lin3_rxd i: can2_rxd ?disabledgp slow/ medium vdd_hv_io b7 gpio flexray cb_tr_en a0: siul_gpio[52] a1: flexray_cb_tr_en a2: _ a3: _ i: _ i: _ i: _ ?disabledgp slow/ symmetric vdd_hv_io b8 gpio flexray ca_tx a0: siul_gpio[48] a1: flexray_ca_tx a2: _ a3: _ i: ctu1_ext_in i: _ i: _ ?disabledgp slow/ symmetric vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 31 b10 gpio fec rxd[3] a0: siul_gpio[214] a1: i2c1_data a2: _ a3: _ i: fec_rxd[3] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io b11 gpio fec rx_er a0: siul_gpio[215] a1: _ a2: _ a3: dspi0_cs1 i: fec_rx_er i: _ i: _ ?disabledgp slow/ medium vdd_hv_io b12 gpio fec rxd[1] a0: siul_gpio[212] a1: dspi1_cs1 a2: etimer2_etc[5] a3: _ i: fec_rxd[1] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io b13 gpio fec tx_er a0: siul_gpio[205] a1: fec_tx_er a2: dspi2_cs3 a3: _ i: flexpwm1_fault[3] i: lin0_rxd i: _ ?disabledgp slow/ medium vdd_hv_io b14 gpio fec tx_clk a0: siul_gpio[207] a1: flexray_dbg0 a2: etimer2_etc[4] a3: dspi0_cs4 i: fec_tx_clk i: _ i: _ ?disabledgp slow/ medium vdd_hv_io b15 gpio can0 txd a0: siul_gpio[16] a1: can0_txd a2: _ a3: sscm_debug[0] i: _ i: _ i: siul_eirq[15] ?disabledgp slow/ medium vdd_hv_io c2 gpio nexus mdo[15] 1 a0: siul_gpio[220] a1: _ a2: npc_wrapper_mdo[15] a3: _ i: can3_rxd i: can2_rxd i: _ ?disabledgp slow/ fast vdd_hv_io c5 gpio flexray cb_rx a0: siul_gpio[50] a1: _ a2: ctu1_ext_tgr a3: _ i: flexray_cb_rx i: _ i: _ ?disabledgp slow/ medium vdd_hv_io c6 gpio etimer0 etc[0] a0: siul_gpio[0] a1: etimer0_etc[0] a2: _ a3: _ i: dspi2_sin i: _ i: siul_eirq[0] ?disabledgp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 32 c7 gpio etimer0 etc[1] a0: siul_gpio[1] a1: etimer0_etc[1] a2: _ a3: _ i: _ i: _ i: siul_eirq[1] ?disabledgp slow/ medium vdd_hv_io c8 gpio etimer0 etc[2] a0: siul_gpio[2] a1: etimer0_etc[2] a2: _ a3: _ i: _ i: _ i: siul_eirq[2] ?disabledgp slow/ medium vdd_hv_io c9 gpio etimer0 etc[3] a0: siul_gpio[3] a1: etimer0_etc[3] a2: _ a3: _ i: _ i: mc_rgm_abs[2] i: siul_eirq[3] ? pulldown gp slow/ medium vdd_hv_io c11 gpio fec crs a0: siul_gpio[208] a1: flexray_dbg1 a2: etimer2_etc[3] a3: dspi0_cs5 i: fec_crs i: _ i: _ ?disabledgp slow/ medium vdd_hv_io c12 gpio fec txd[0] a0: siul_gpio[201] a1: fec_txd[0] a2: etimer2_etc[1] a3: _ i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io c13 gpio fec col a0: siul_gpio[206] a1: fec_col a2: _ a3: lin1_txd i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io c14 gpio can0 rxd a0: siul_gpio[17] a1: _ a2: _ a3: sscm_debug[1] i: can0_rxd i: can1_rxd i: siul_eirq[16] ?disabledgp slow/ medium vdd_hv_io c16 gpio pdi data[5] a0: siul_gpio[136] a1: flexpwm2_a[0] a2: _ a3: etimer1_etc[0] i: pdi_data[5] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c17 gpio pdi clock a0: siul_gpio[128] a1: flexpwm2_b[1] a2: _ a3: etimer1_etc[3] i: pdi_clock i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 33 d1 gpio nexus mdo[2] 1 a0: siul_gpio[85] a1: _ a2: npc_wrapper_mdo[2] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io d2 gpio nexus mdo[3] 1 a0: siul_gpio[84] a1: _ a2: npc_wrapper_mdo[3] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io d3 gpio can1 rxd a0: siul_gpio[15] a1: _ a2: _ a3: _ i: can1_rxd i: can0_rxd i: siul_eirq[14] ?disabledgp slow/ medium vdd_hv_io d4 gpio dspi0 sout a0: siul_gpio[38] a1: dspi0_sout a2: _ a3: sscm_debug[6] i: _ i: _ i: siul_eirq[24] ?disabledgp slow/ medium vdd_hv_io d6 gpio etimer0 etc[5] a0: siul_gpio[44] a1: etimer0_etc[5] a2: _ a3: _ i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io d7 gpio etimer0 etc[4] a0: siul_gpio[43] a1: etimer0_etc[4] a2: _ a3: _ i: _ i: mc_rgm_abs[0] i: _ ? pulldown gp slow/ medium vdd_hv_io d10 gpio fec txd[2] a0: siul_gpio[203] a1: fec_txd[2] a2: _ a3: _ i: flexpwm1_fault[1] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io d11 gpio fec txd[1] a0: siul_gpio[202] a1: fec_txd[1] a2: _ a3: dspi2_sck i: flexpwm1_fault[0] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io d12 gpio fec rx_dv a0: siul_gpio[210] a1: flexray_dbg3 a2: etimer2_etc[0] a3: dspi0_cs7 i: fec_rx_dv i: _ i: _ ?disabledgp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 34 d13 gpio fec mdc a0: siul_gpio[199] a1: fec_mdc a2: _ a3: _ i: _ i: lin1_rxd i: _ ?disabledgp slow/ medium vdd_hv_io d16 gpio pdi data[0] a0: siul_gpio[131] a1: _ a2: lin3_txd a3: _ i: pdi_data[0] i: _ i: flexpwm2_fault[2] ? disabled pdi medium vdd_hv_pdi d17 gpio pdi data[1] a0: siul_gpio[132] a1: flexpwm2_b[3] a2: _ a3: _ i: pdi_data[1] i: _ i: _ ? disabled pdi medium vdd_hv_pdi e2 gpio nexus mdo[1] 1 a0: siul_gpio[86] a1: _ a2: npc_wrapper_mdo[1] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io e3 gpio flexray ca_rx a0: siul_gpio[49] a1: _ a2: ctu0_ext_tgr a3: _ i: flexray_ca_rx i: _ i: _ ?disabledgp slow/ medium vdd_hv_io e14 gpio pdi line_v a0: siul_gpio[129] a1: _ a2: lin2_txd a3: _ i: pdi_line_v i: _ i: flexpwm2_fault[0] ? disabled pdi medium vdd_hv_pdi e15 gpio pdi data[2] a0: siul_gpio[133] a1: flexpwm2_a[1] a2: _ a3: etimer1_etc[2] i: pdi_data[2] i: _ i: _ ? disabled pdi medium vdd_hv_pdi e16 gpio pdi data[3] a0: siul_gpio[134] a1: flexpwm2_x[1] a2: _ a3: _ i: pdi_data[3] i: _ i: _ ? disabled pdi medium vdd_hv_pdi e17 gpio pdi data[4] a0: siul_gpio[135] a1: flexpwm2_a[2] a2: _ a3: etimer1_etc[4] i: pdi_data[4] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 35 f1 gpio nexus mdo[6] 1 a0: siul_gpio[113] a1: _ a2: npc_wrapper_mdo[6] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io f2 gpio nexus mdo[11] 1 a0: siul_gpio[108] a1: _ a2: npc_wrapper_mdo[11] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io f3 gpio dspi1 sout a0: siul_gpio[7] a1: dspi1_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[7] ?disabledgp slow/ medium vdd_hv_io f4 gpio dspi1 sin a0: siul_gpio[8] a1: _ a2: _ a3: _ i: dspi1_sin i: _ i: siul_eirq[8] ?disabledgp slow/ medium vdd_hv_io f14 gpio mc_cgl clk_out a0: siul_gpio[233] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: _ ? disabled pdi fast vdd_hv_pdi f15 gpio pdi data[6] a0: siul_gpio[137] a1: flexpwm2_b[0] a2: _ a3: etimer1_etc[1] i: pdi_data[6] i: _ i: _ ? disabled pdi medium vdd_hv_pdi f16 gpio pdi data[7] a0: siul_gpio[138] a1: flexpwm2_b[2] a2: _ a3: etimer1_etc[5] i: pdi_data[7] i: _ i: _ ? disabled pdi medium vdd_hv_pdi f17 gpio pdi data[8] a0: siul_gpio[139] a1: flexpwm2_a[3] a2: _ a3: _ i: pdi_data[8] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g1 gpio nexus mdo[4] 1 a0: siul_gpio[115] a1: _ a2: npc_wrapper_mdo[4] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 36 g3 gpio dspi0 sck a0: siul_gpio[37] a1: dspi0_sck a2: _ a3: sscm_debug[5] i: flexpwm0_fault[3] i: _ i: siul_eirq[23] ?disabledgp slow/ medium vdd_hv_io g4 gpio dspi1 sck a0: siul_gpio[6] a1: dspi1_sck a2: _ a3: _ i: _ i: _ i: siul_eirq[6] ?disabledgp slow/ medium vdd_hv_io g14 gpio pdi data[9] a0: siul_gpio[140] a1: flexpwm2_x[2] a2: _ a3: _ i: pdi_data[9] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g15 gpio pdi data[10] a0: siul_gpio[141] a1: flexpwm2_x[3] a2: _ a3: _ i: pdi_data[10] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g16 gpio pdi data[11] a0: siul_gpio[142] a1: flexpwm2_x[0] a2: _ a3: _ i: pdi_data[11] i: _ i: _ ? disabled pdi medium vdd_hv_pdi g17 gpio pdi frame_v a0: siul_gpio[130] a1: _ a2: _ a3: _ i: pdi_frame_v i: lin2_rxd i: flexpwm2_fault[1] ? disabled pdi medium vdd_hv_pdi h1 gpio nexus mdo[10] 1 a0: siul_gpio[109] a1: _ a2: npc_wrapper_mdo[10] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io h3 gpio dspi0 cs0 a0: siul_gpio[36] a1: dspi0_cs0 a2: _ a3: sscm_debug[4] i: _ i: _ i: siul_eirq[22] ?disabledgp slow/ medium vdd_hv_io h4 gpio dspi1 cs0 a0: siul_gpio[5] a1: dspi1_cs0 a2: _ a3: dspi0_cs7 i: _ i: _ i: siul_eirq[5] ?disabledgp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 37 h14 gpio pdi data[12] a0: siul_gpio[143] a1: _ a2: _ a3: _ i: pdi_data[12] i: lin3_rxd i: flexpwm2_fault[3] ? disabled pdi medium vdd_hv_pdi h15 gpio pdi data[13] a0: siul_gpio[144] a1: pdi_sens_sel[2] a2: ctu1_ext_tgr a3: _ i: pdi_data[13] i: _ i: _ ? disabled pdi medium vdd_hv_pdi h17 gpio flexpwm0 x[0] a0: siul_gpio[194] a1: flexpwm0_x[0] a2: ebi_ad28 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io j1 gpio nexus mcko a0: siul_gpio[87] a1: _ a2: npc_wrapper_mcko a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io j2 gpio nexus mdo[8] 1 a0: siul_gpio[111] a1: _ a2: npc_wrapper_mdo[8] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io j3 gpio dspi2 cs0 a0: siul_gpio[10] a1: dspi2_cs0 a2: _ a3: can3_txd i: _ i: _ i: siul_eirq[9] ?disabledgp slow/ medium vdd_hv_io j4 gpio dspi2 cs2 a0: siul_gpio[42] a1: dspi2_cs2 a2: lin3_txd a3: can2_txd i: flexpwm0_fault[1] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io j14 gpio pdi data[14] a0: siul_gpio[145] a1: pdi_sens_sel[1] a2: i2c2_clock a3: _ i: pdi_data[14] i: _ i: _ ? disabled pdi medium vdd_hv_pdi j15 gpio pdi data[15] a0: siul_gpio[146] a1: pdi_sens_sel[0] a2: i2c2_data a3: _ i: pdi_data[15] i: ctu1_ext_in i: _ ? disabled pdi medium vdd_hv_pdi table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 38 j17 gpio flexpwm0 x[1] a0: siul_gpio[195] a1: flexpwm0_x[1] a2: ebi_ad29 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k1 gpio nexus mseo_b[0] 1 a0: siul_gpio[89] a1: _ a2: npc_wrapper_mseo_b[0] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io k2 gpio nexus mseo_b[1] 1 a0: siul_gpio[88] a1: _ a2: npc_wrapper_mseo_b[1] a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io k3 gpio nexus rdy_b a0: siul_gpio[216] a1: _ a2: nexus_rdy_b a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io k4 gpio dspi0 sin a0: siul_gpio[39] a1: _ a2: _ a3: sscm_debug[7] i: dspi0_sin i: _ i: _ ?disabledgp slow/ medium vdd_hv_io k14 gpio flexpwm0 x[2] a0: siul_gpio[196] a1: flexpwm0_x[2] a2: ebi_ad30 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k15 gpio flexpwm0 x[3] a0: siul_gpio[197] a1: flexpwm0_x[3] a2: ebi_ad31 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k16 gpio flexpwm0 a[1] a0: siul_gpio[149] a1: _ a2: ebi_rd_wr a3: flexpwm0_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io k17 gpio flexpwm0 b[0] a0: siul_gpio[148] a1: _ a2: ebi_clkout a3: flexpwm0_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 39 l1 gpio nexus evto_b a0: siul_gpio[90] a1: _ a2: npc_wrapper_evto_b a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io l2 gpio nexus evti_b a0: siul_gpio[91] a1: _ a2: leo_sor_proxy_evti_b a3: _ i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io l3 gpio dspi2 sck a0: siul_gpio[11] a1: dspi2_sck a2: _ a3: _ i: can3_rxd i: _ i: siul_eirq[10] ?disabledgp slow/ medium vdd_hv_io l4 gpio nexus mdo[13] 1 a0: siul_gpio[218] a1: _ a2: npc_wrapper_mdo[13] a3: _ i: can2_rxd i: can3_rxd i: _ ?disabledgp slow/ fast vdd_hv_io l16 gpio flexpwm0 b[1] a0: siul_gpio[150] a1: dramc_cs0 a2: ebi_ts a3: flexpwm0_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io l17 gpio tdo a0: siul_gpio[20] a1: jtagc_tdo a2: _ a3: _ i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io m3 gpio dspi1 cs2 a0: siul_gpio[56] a1: dspi1_cs2 a2: _ a3: dspi0_cs5 i: flexpwm0_fault[3] i: lin2_rxd i: _ ?disabledgp slow/ medium vdd_hv_io m4 gpio nexus mdo[12] 1 a0: siul_gpio[217] a1: _ a2: npc_wrapper_mdo[12] a3: can2_txd i: _ i: _ i: _ ?disabledgp slow/ fast vdd_hv_io m14 gpio flexpwm0 b[2] a0: siul_gpio[152] a1: dramc_cas a2: ebi_we_be_1 a3: flexpwm0_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 40 m15 gpio tdi a0: siul_gpio[21] a1: _ a2: _ a3: _ i: jtagc_tdi i: _ i: _ ? pullup gp slow/ medium vdd_hv_io m17 gpio flexpwm1 a[1] a0: siul_gpio[157] a1: dramc_odt a2: ebi_cs1 a3: flexpwm1_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n3 gpio dspi0 cs3 a0: siul_gpio[53] a1: dspi0_cs3 a2: i2c2_clock a3: _ i: flexpwm0_fault[2] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io n14 gpio flexpwm0 b[3] a0: siul_gpio[154] a1: dramc_ba[0] a2: ebi_we_be_3 a3: flexpwm0_b[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n15 gpio flexpwm0 a[2] a0: siul_gpio[151] a1: dramc_ras a2: ebi_we_be_0 a3: flexpwm0_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n16 gpio flexpwm1 a[0] a0: siul_gpio[155] a1: dramc_ba[1] a2: ebi_bdip a3: flexpwm1_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io n17 gpio flexpwm1 b[0] a0: siul_gpio[156] a1: dramc_ba[2] a2: ebi_cs0 a3: flexpwm1_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io p3 gpio dspi0 cs2 a0: siul_gpio[54] a1: dspi0_cs2 a2: i2c2_data a3: _ i: flexpwm0_fault[1] i: _ i: _ ?disabledgp slow/ medium vdd_hv_io p5 gpio etimer1 etc[1] a0: siul_gpio[45] a1: etimer1_etc[1] a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: ctu1_ext_in ?disabledgp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 41 p6 gpio etimer1 etc[2] a0: siul_gpio[46] a1: etimer1_etc[2] a2: ctu0_ext_tgr a3: _ i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io p7 ana adc0 an[0] ? siul_gpi[23] lin0_rxd an: adc0_an[0] analog vdd_hv_adr02 p8 gpio etimer1 etc[3] a0: siul_gpio[92] a1: etimer1_etc[3] a2: _ a3: _ i: ctu1_ext_in i: mc_rgm_fab i: siul_eirq[30] ? pulldown gp slow/ medium vdd_hv_io p11 ana adc0_adc1 an[14] ? siul_gpi[28] an: adc0_adc1_an[14] analog shared vdd_hv_adr02 p12 gpio etimer1 etc[4] a0: siul_gpio[93] a1: etimer1_etc[4] a2: ctu1_ext_tgr a3: _ i: _ i: _ i: siul_eirq[31] ?disabledgp slow/ medium vdd_hv_io p13 gpio etimer1 etc[5] a0: siul_gpio[78] a1: etimer1_etc[5] a2: _ a3: _ i: _ i: _ i: siul_eirq[26] ?disabledgp slow/ medium vdd_hv_io p15 gpio flexpwm0 a[3] a0: siul_gpio[153] a1: dramc_web a2: ebi_we_be_2 a3: flexpwm0_a[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io p16 gpio flexpwm0 a[0] a0: siul_gpio[147] a1: dramc_cke a2: ebi_oe a3: flexpwm0_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io p17 gpio flexpwm1 b[1] a0: siul_gpio[163] a1: dramc_add[5] a2: ebi_add13 a3: flexpwm1_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 42 r4 gpio dspi1 cs3 a0: siul_gpio[55] a1: dspi1_cs3 a2: lin2_txd a3: dspi0_cs4 i: _ i: _ i: _ ?disabledgp slow/ medium vdd_hv_io r5 ana adc2 an[0] ? siul_gpi[221] an: adc2_an[0] ? analog vdd_hv_adr02 r6 ana adc2 an[3] ? siul_gpi[224] an: adc2_an[3] ? analog vdd_hv_adr02 r8 ana adc2_adc3 an[14] ? siul_gpi[228] an: adc2_adc3_an[14] ? analog shared vdd_hv_adr13 r10 ana adc0 an[2] ? siul_gpi[33] an: adc0_an[2] ? analog vdd_hv_adr02 r11 ana adc0_adc1 an[13] ? siul_gpi[27] an: adc0_adc1_an[13] ? analog shared vdd_hv_adr02 r12 ana adc1 an[1] ? siul_gpi[30] etimer0_etc[4] siul_eirq[19] an: adc1_an[1] ? analog vdd_hv_adr13 r14 gpio lin0 txd a0: siul_gpio[18] a1: lin0_txd a2: i2c0_clock a3: sscm_debug[2] i: _ i: _ i: siul_eirq[17] ?disabledgp slow/ medium vdd_hv_io r16 gpio flexpwm1 a[2] a0: siul_gpio[164] a1: dramc_add[6] a2: ebi_add14 a3: flexpwm1_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io r17 gpio flexpwm1 b[2] a0: siul_gpio[165] a1: dramc_add[7] a2: ebi_add15 a3: flexpwm1_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 43 t3 gpio dspi2 sout a0: siul_gpio[12] a1: dspi2_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[11] ?disabledgp slow/ medium vdd_hv_io t4 ana adc3 an[0] ? siul_gpi[229] an: adc3_an[0] ? analog vdd_hv_adr13 t5 ana adc3 an[3] ? siul_gpi[232] an: adc3_an[3] ? analog vdd_hv_adr13 t6 ana adc2 an[2] ? siul_gpi[223] an: adc2_an[2] ? analog vdd_hv_adr02 t8 ana adc2_adc3 an[13] ? siul_gpi[227] an: adc2_adc3_an[13] ? analog shared vdd_hv_adr02 t10 ana adc0 an[1] ? siul_gpi[24] etimer0_etc[5] an: adc0_an[1] ? analog vdd_hv_adr02 t11 ana adc0_adc1 an[12] ? siul_gpi[26] an: adc0_adc1_an[12] ? analog shared vdd_hv_adr02 t12 ana adc1 an[0] ? siul_gpi[29] lin1_rxd an: adc1_an[0] ? analog vdd_hv_adr13 t13 ana adc1 an[2] ? siul_gpi[31] siul_eirq[20] an: adc1_an[2] ? analog vdd_hv_adr13 t14 gpio lin0 rxd a0: siul_gpio[19] a1: _ a2: i2c0_data a3: sscm_debug[3] i: lin0_rxd i: _ i: _ ?disabledgp slow/ medium vdd_hv_io table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 44 t15 gpio etimer1 etc[0] a0: siul_gpio[4] a1: etimer1_etc[0] a2: _ a3: _ i: _ i: _ i: siul_eirq[4] ?disabledgp slow/ medium vdd_hv_io u3 gpio dspi2 sin a0: siul_gpio[13] a1: _ a2: _ a3: _ i: dspi2_sin i: flexpwm0_fault[0] i: siul_eirq[12] ?disabledgp slow/ medium vdd_hv_io u4 ana adc3 an[1] ? siul_gpi[230] an: adc3_an[1] ? analog vdd_hv_adr13 u5 ana adc3 an[2] ? siul_gpi[231] an: adc3_an[2] ? analog vdd_hv_adr13 u6 ana adc2 an[1] ? siul_gpi[222] an: adc2_an[1] ? analog vdd_hv_adr02 u7 ana adc2_adc3 an[11] ? siul_gpi[225] an: adc2_adc3_an[11] ? analog shared vdd_hv_adr13 u8 ana adc2_adc3 an[12] ? siul_gpi[226] an: adc2_adc3_an[12] ? analog shared vdd_hv_adr13 u11 ana adc0_adc1 an[11] ? siul_gpi[25] an: adc0_adc1_an[11] ? analog shared vdd_hv_adr02 end of 257 mapbga pin multiplexing table 1 do not connect pin directly to a power supply or ground. table 9. 257 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 45 table 10. 473 mapbga pin multiplexing ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain a4 gpio nexus mdo[5] 1 a0: siul_gpio[114] a1: _ a2: npc_wrapper_mdo[5] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a5 gpio nexus mdo[7] 1 a0: siul_gpio[112] a1: _ a2: npc_wrapper_mdo[7] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a6 gpio nexus mdo[9] 1 a0: siul_gpio[110] a1: _ a2: npc_wrapper_mdo[9] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io a7 gpio flexray cb_tx a0: siul_gpio[51] a1: flexray_cb_tx a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io a8 gpio flexray ca_tr_en a0: siul_gpio[47] a1: flexray_ca_tr_en a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: _ ? disabled gp slow/ symmetric vdd_hv_io a9 gpio fec rx_dv a0: siul_gpio[210] a1: flexray_dbg3 a2: etimer2_etc[0] a3: dspi0_cs7 i: fec_rx_dv i: _ i: _ ? disabled gp slow/ medium vdd_hv_io a10 gpio fec mdio a0: siul_gpio[198] a1: fec_mdio a2: _ a3: dspi2_cs0 i: _ i: _ i: siul_eirq[28] ? disabled gp slow/ medium vdd_hv_io a11 gpio fec tx_clk a0: siul_gpio[207] a1: flexray_dbg0 a2: etimer2_etc[4] a3: dspi0_cs4 i: fec_tx_clk i: _ i: _ ? disabled gp slow/ medium vdd_hv_io a12 gpio fec tx_en a0: siul_gpio[200] a1: fec_tx_en a2: _ a3: lin0_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 46 a13 gpio fec txd[3] a0: siul_gpio[204] a1: fec_txd[3] a2: _ a3: dspi2_cs2 i: flexpwm1_fault[2] i: _ i: siul_eirq[29] ? disabled gp slow/ medium vdd_hv_io a15 gpio pdi data[3] a0: siul_gpio[134] a1: flexpwm2_x[1] a2: _ a3: _ i: pdi_data[3] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a16 gpio pdi data[1] a0: siul_gpio[132] a1: flexpwm2_b[3] a2: _ a3: _ i: pdi_data[1] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a17 gpio pdi clock a0: siul_gpio[128] a1: flexpwm2_b[1] a2: _ a3: etimer1_etc[3] i: pdi_clock i: _ i: _ ? disabled pdi medium vdd_hv_pdi a18 gpio pdi data[7] a0: siul_gpio[138] a1: flexpwm2_b[2] a2: _ a3: etimer1_etc[5] i: pdi_data[7] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a19 gpio pdi data[10] a0: siul_gpio[141] a1: flexpwm2_x[3] a2: _ a3: _ i: pdi_data[10] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a20 gpio pdi data[13] a0: siul_gpio[144] a1: pdi_sens_sel[2] a2: ctu1_ext_tgr a3: _ i: pdi_data[13] i: _ i: _ ? disabled pdi medium vdd_hv_pdi a21 gpio pdi data[15] a0: siul_gpio[146] a1: pdi_sens_sel[0] a2: i2c2_data a3: _ i: pdi_data[15] i: ctu1_ext_in i: _ ? disabled pdi medium vdd_hv_pdi b3 gpio mc_cgl clk_out a0: siul_gpio[22] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: siul_eirq[18] ? disabled gp slow/ fast vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 47 b4 gpio can1 txd a0: siul_gpio[14] a1: can1_txd a2: _ a3: _ i: _ i: _ i: siul_eirq[13] ? disabled gp slow/ medium vdd_hv_io b5 gpio nexus mdo[14] 1 a0: siul_gpio[219] a1: _ a2: npc_wrapper_mdo[14] a3: can3_txd i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io b6 gpio dspi2 cs1 a0: siul_gpio[9] a1: dspi2_cs1 a2: _ a3: _ i: flexpwm0_fault[0] i: lin3_rxd i: can2_rxd ? disabled gp slow/ medium vdd_hv_io b7 gpio flexray cb_tr_en a0: siul_gpio[52] a1: flexray_cb_tr_en a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io b8 gpio flexray ca_tx a0: siul_gpio[48] a1: flexray_ca_tx a2: _ a3: _ i: ctu1_ext_in i: _ i: _ ? disabled gp slow/ symmetric vdd_hv_io b9 gpio fec rxd[3] a0: siul_gpio[214] a1: i2c1_data a2: _ a3: _ i: fec_rxd[3] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b10 gpio fec rx_er a0: siul_gpio[215] a1: _ a2: _ a3: dspi0_cs1 i: fec_rx_er i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b11 gpio fec txd[0] a0: siul_gpio[201] a1: fec_txd[0] a2: etimer2_etc[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io b12 gpio fec rxd[0] a0: siul_gpio[211] a1: i2c1_clock a2: _ a3: _ i: fec_rxd[0] i: _ i: siul_eirq[27] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 48 b13 gpio fec tx_er a0: siul_gpio[205] a1: fec_tx_er a2: dspi2_cs3 a3: _ i: flexpwm1_fault[3] i: lin0_rxd i: _ ? disabled gp slow/ medium vdd_hv_io b15 gpio pdi data[6] a0: siul_gpio[137] a1: flexpwm2_b[0] a2: _ a3: etimer1_etc[1] i: pdi_data[6] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b16 gpio pdi data[4] a0: siul_gpio[135] a1: flexpwm2_a[2] a2: _ a3: etimer1_etc[4] i: pdi_data[4] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b17 gpio pdi data[0] a0: siul_gpio[131] a1: _ a2: lin3_txd a3: _ i: pdi_data[0] i: _ i: flexpwm2_fault[2] ? disabled pdi medium vdd_hv_pdi b18 gpio pdi line_v a0: siul_gpio[129] a1: _ a2: lin2_txd a3: _ i: pdi_line_v i: _ i: flexpwm2_fault[0] ? disabled pdi medium vdd_hv_pdi b19 gpio pdi data[9] a0: siul_gpio[140] a1: flexpwm2_x[2] a2: _ a3: _ i: pdi_data[9] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b20 gpio pdi data[14] a0: siul_gpio[145] a1: pdi_sens_sel[1] a2: i2c2_clock a3: _ i: pdi_data[14] i: _ i: _ ? disabled pdi medium vdd_hv_pdi b21 gpio can0 txd a0: siul_gpio[16] a1: can0_txd a2: _ a3: sscm_debug[0] i: _ i: _ i: siul_eirq[15] ? disabled gp slow/ medium vdd_hv_io c2 gpio nexus mdo[15] 1 a0: siul_gpio[220] a1: _ a2: npc_wrapper_mdo[15] a3: _ i: can3_rxd i: can2_rxd i: _ ? disabled gp slow/ fast vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 49 c5 gpio flexray cb_rx a0: siul_gpio[50] a1: _ a2: ctu1_ext_tgr a3: _ i: flexray_cb_rx i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c6 gpio etimer0 etc[4] a0: siul_gpio[43] a1: etimer0_etc[4] a2: _ a3: _ i: _ i: mc_rgm_abs[0] i: _ ? pulldown gp slow/ medium vdd_hv_io c7 gpio etimer0 etc[1] a0: siul_gpio[1] a1: etimer0_etc[1] a2: _ a3: _ i: _ i: _ i: siul_eirq[1] ? disabled gp slow/ medium vdd_hv_io c8 gpio etimer0 etc[2] a0: siul_gpio[2] a1: etimer0_etc[2] a2: _ a3: _ i: _ i: _ i: siul_eirq[2] ? disabled gp slow/ medium vdd_hv_io c9 gpio etimer0 etc[3] a0: siul_gpio[3] a1: etimer0_etc[3] a2: _ a3: _ i: _ i: mc_rgm_abs[2] i: siul_eirq[3] ? pulldown gp slow/ medium vdd_hv_io c10 gpio fec txd[2] a0: siul_gpio[203] a1: fec_txd[2] a2: _ a3: _ i: flexpwm1_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c11 gpio fec txd[1] a0: siul_gpio[202] a1: fec_txd[1] a2: _ a3: dspi2_sck i: flexpwm1_fault[0] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c12 gpio fec crs a0: siul_gpio[208] a1: flexray_dbg1 a2: etimer2_etc[3] a3: dspi0_cs5 i: fec_crs i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c13 gpio fec rx_clk a0: siul_gpio[209] a1: flexray_dbg2 a2: etimer2_etc[2] a3: dspi0_cs6 i: fec_rx_clk i: _ i: siul_eirq[25] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 50 c14 gpio fec rxd[1] a0: siul_gpio[212] a1: dspi1_cs1 a2: etimer2_etc[5] a3: _ i: fec_rxd[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c15 gpio fec col a0: siul_gpio[206] a1: fec_col a2: _ a3: lin1_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io c16 gpio pdi data[5] a0: siul_gpio[136] a1: flexpwm2_a[0] a2: _ a3: etimer1_etc[0] i: pdi_data[5] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c17 gpio pdi data[2] a0: siul_gpio[133] a1: flexpwm2_a[1] a2: _ a3: etimer1_etc[2] i: pdi_data[2] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c18 gpio pdi data[8] a0: siul_gpio[139] a1: flexpwm2_a[3] a2: _ a3: _ i: pdi_data[8] i: _ i: _ ? disabled pdi medium vdd_hv_pdi c19 gpio pdi data[12] a0: siul_gpio[143] a1: _ a2: _ a3: _ i: pdi_data[12] i: lin3_rxd i: flexpwm2_fault[3] ? disabled pdi medium vdd_hv_pdi c20 gpio can0 rxd a0: siul_gpio[17] a1: _ a2: _ a3: sscm_debug[1] i: can0_rxd i: can1_rxd i: siul_eirq[16] ? disabled gp slow/ medium vdd_hv_io c22 gpio siul gpio[197] a0: siul_gpio[197] a1: flexpwm0_x[3] a2: ebi_ad31 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram c23 gpio dramc cas a0: siul_gpio[152] a1: dramc_cas a2: ebi_we_be_1 a3: flexpwm0_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 51 d1 gpio nexus mdo[1] 1 a0: siul_gpio[86] a1: _ a2: npc_wrapper_mdo[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io d2 gpio nexus mdo[3] 1 a0: siul_gpio[84] a1: _ a2: npc_wrapper_mdo[3] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io d3 gpio can1 rxd a0: siul_gpio[15] a1: _ a2: _ a3: _ i: can1_rxd i: can0_rxd i: siul_eirq[14] ? disabled gp slow/ medium vdd_hv_io d4 gpio dspi0 sout a0: siul_gpio[38] a1: dspi0_sout a2: _ a3: sscm_debug[6] i: _ i: _ i: siul_eirq[24] ? disabled gp slow/ medium vdd_hv_io d6 gpio etimer0 etc[5] a0: siul_gpio[44] a1: etimer0_etc[5] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io d7 gpio etimer0 etc[0] a0: siul_gpio[0] a1: etimer0_etc[0] a2: _ a3: _ i: dspi2_sin i: _ i: siul_eirq[0] ? disabled gp slow/ medium vdd_hv_io d14 gpio fec rxd[2] a0: siul_gpio[213] a1: _ a2: _ a3: dspi2_sout i: fec_rxd[2] i: _ i: siul_eirq[21] ? disabled gp slow/ medium vdd_hv_io d15 gpio fec mdc a0: siul_gpio[199] a1: fec_mdc a2: _ a3: _ i: _ i: lin1_rxd i: _ ? disabled gp slow/ medium vdd_hv_io d18 gpio pdi data[11] a0: siul_gpio[142] a1: flexpwm2_x[0] a2: _ a3: _ i: pdi_data[11] i: _ i: _ ? disabled pdi medium vdd_hv_pdi table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 52 d19 gpio pdi frame_v a0: siul_gpio[130] a1: _ a2: _ a3: _ i: pdi_frame_v i: lin2_rxd i: flexpwm2_fault[1] ? disabled pdi medium vdd_hv_pdi d21 gpio dramc ba[1] a0: siul_gpio[155] a1: dramc_ba[1] a2: ebi_bdip a3: flexpwm1_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram d22 gpio siul gpio[195] a0: siul_gpio[195] a1: flexpwm0_x[1] a2: ebi_ad29 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram d23 gpio dramc ba[0] a0: siul_gpio[154] a1: dramc_ba[0] a2: ebi_we_be_3 a3: flexpwm0_b[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram e2 gpio nexus mdo[2] 1 a0: siul_gpio[85] a1: _ a2: npc_wrapper_mdo[2] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io e3 gpio flexray ca_rx a0: siul_gpio[49] a1: _ a2: ctu0_ext_tgr a3: _ i: flexray_ca_rx i: _ i: _ ? disabled gp slow/ medium vdd_hv_io e20 gpio mc_cgl clk_out a0: siul_gpio[233] a1: mc_cgl_clk_out a2: etimer2_etc[5] a3: _ i: _ i: _ i: _ ? disabled pdi fast vdd_hv_pdi e21 gpio siul gpio[149] a0: siul_gpio[149] a1: _ a2: ebi_rd_wr a3: flexpwm0_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram e22 gpio dramc cs0 a0: siul_gpio[150] a1: dramc_cs0 a2: ebi_ts a3: flexpwm0_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 53 e23 gpio dramc ba[2] a0: siul_gpio[156] a1: dramc_ba[2] a2: ebi_cs0 a3: flexpwm1_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f1 gpio nexus mdo[10] 1 a0: siul_gpio[109] a1: _ a2: npc_wrapper_mdo[10] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f2 gpio nexus mdo[11] 1 a0: siul_gpio[108] a1: _ a2: npc_wrapper_mdo[11] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f3 gpio nexus mdo[6] 1 a0: siul_gpio[113] a1: _ a2: npc_wrapper_mdo[6] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f4 gpio nexus mdo[4] 1 a0: siul_gpio[115] a1: _ a2: npc_wrapper_mdo[4] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io f20 gpio dramc ras a0: siul_gpio[151] a1: dramc_ras a2: ebi_we_be_0 a3: flexpwm0_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f21 gpio siul gpio[194] a0: siul_gpio[194] a1: flexpwm0_x[0] a2: ebi_ad28 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f22 gpio siul gpio[148] a0: siul_gpio[148] a1: _ a2: ebi_clkout a3: flexpwm0_b[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram f23 gpio dramc d[5] a0: siul_gpio[179] a1: dramc_d[5] a2: ebi_ad13 a3: ebi_add29 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 54 g1 gpio nexus mcko a0: siul_gpio[87] a1: _ a2: npc_wrapper_mcko a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g3 gpio nexus mdo[8] 1 a0: siul_gpio[111] a1: _ a2: npc_wrapper_mdo[8] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g4 gpio nexus mseo_b[1] 1 a0: siul_gpio[88] a1: _ a2: npc_wrapper_mseo_b[1] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io g20 gpio siul gpio[196] a0: siul_gpio[196] a1: flexpwm0_x[2] a2: ebi_ad30 a3: _ i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram g21 gpio dramc dqs[0] a0: siul_gpio[190] a1: dramc_dqs[0] a2: ebi_ad24 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram g22 gpio dramc dm[0] a0: siul_gpio[192] a1: dramc_dm[0] a2: ebi_ad26 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram g23 gpio dramc d[7] a0: siul_gpio[181] a1: dramc_d[7] a2: ebi_ad15 a3: ebi_add31 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram h1 gpio nexus evto_b a0: siul_gpio[90] a1: _ a2: npc_wrapper_evto_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io h3 gpio nexus mseo_b[0] 1 a0: siul_gpio[89] a1: _ a2: npc_wrapper_mseo_b[0] a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 55 h4 gpio nexus evti_b a0: siul_gpio[91] a1: _ a2: leo_sor_proxy_evti_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io h20 gpio dramc d[2] a0: siul_gpio[176] a1: dramc_d[2] a2: ebi_ad10 a3: ebi_add26 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram j1 gpio nexus rdy_b a0: siul_gpio[216] a1: _ a2: nexus_rdy_b a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io j2 gpio nexus mdo[13] 1 a0: siul_gpio[218] a1: _ a2: npc_wrapper_mdo[13] a3: _ i: can2_rxd i: can3_rxd i: _ ? disabled gp slow/ fast vdd_hv_io j3 gpio nexus mdo[12] 1 a0: siul_gpio[217] a1: _ a2: npc_wrapper_mdo[12] a3: can2_txd i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io j4 gpio dspi1 sin a0: siul_gpio[8] a1: _ a2: _ a3: _ i: dspi1_sin i: _ i: siul_eirq[8] ? disabled gp slow/ medium vdd_hv_io j20 gpio dramc d[0] a0: siul_gpio[174] a1: dramc_d[0] a2: ebi_ad8 a3: ebi_add24 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram j21 gpio dramc d[1] a0: siul_gpio[175] a1: dramc_d[1] a2: ebi_ad9 a3: ebi_add25 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram j22 gpio dramc d[3] a0: siul_gpio[177] a1: dramc_d[3] a2: ebi_ad11 a3: ebi_add27 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 56 j23 gpio dramc d[6] a0: siul_gpio[180] a1: dramc_d[6] a2: ebi_ad14 a3: ebi_add30 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram k1 gpio dspi0 sck a0: siul_gpio[37] a1: dspi0_sck a2: _ a3: sscm_debug[5] i: flexpwm0_fault[3] i: _ i: siul_eirq[23] ? disabled gp slow/ medium vdd_hv_io k2 gpio dspi1 cs0 a0: siul_gpio[5] a1: dspi1_cs0 a2: _ a3: dspi0_cs7 i: _ i: _ i: siul_eirq[5] ? disabled gp slow/ medium vdd_hv_io k3 gpio dspi1 sck a0: siul_gpio[6] a1: dspi1_sck a2: _ a3: _ i: _ i: _ i: siul_eirq[6] ? disabled gp slow/ medium vdd_hv_io k4 gpio dspi1 sout a0: siul_gpio[7] a1: dspi1_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[7] ? disabled gp slow/ medium vdd_hv_io k21 gpio dramc d[4] a0: siul_gpio[178] a1: dramc_d[4] a2: ebi_ad12 a3: ebi_add28 i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram k22 gpio dramc d[8] a0: siul_gpio[182] a1: dramc_d[8] a2: ebi_ad16 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram k23 gpio dramc d[9] a0: siul_gpio[183] a1: dramc_d[9] a2: ebi_ad17 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram l1 gpio dspi0 cs0 a0: siul_gpio[36] a1: dspi0_cs0 a2: _ a3: sscm_debug[4] i: _ i: _ i: siul_eirq[22] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 57 l2 gpio dspi2 cs2 a0: siul_gpio[42] a1: dspi2_cs2 a2: lin3_txd a3: can2_txd i: flexpwm0_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io l3 gpio dspi2 cs0 a0: siul_gpio[10] a1: dspi2_cs0 a2: _ a3: can3_txd i: _ i: _ i: siul_eirq[9] ? disabled gp slow/ medium vdd_hv_io m1 gpio flexpwm0 x[0] a0: siul_gpio[57] a1: flexpwm0_x[0] a2: lin2_txd a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io m3 gpio dspi0 sin a0: siul_gpio[39] a1: _ a2: _ a3: sscm_debug[7] i: dspi0_sin i: _ i: _ ? disabled gp slow/ medium vdd_hv_io m20 gpio dramc odt a0: siul_gpio[157] a1: dramc_odt a2: ebi_cs1 a3: flexpwm1_a[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram m21 gpio dramc web a0: siul_gpio[153] a1: dramc_web a2: ebi_we_be_2 a3: flexpwm0_a[3] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram m22 gpio dramc d[11] a0: siul_gpio[185] a1: dramc_d[11] a2: ebi_ad19 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram m23 gpio dramc d[10] a0: siul_gpio[184] a1: dramc_d[10] a2: ebi_ad18 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n1 gpio flexpwm0 a[0] a0: siul_gpio[58] a1: flexpwm0_a[0] a2: _ a3: _ i: _ i: etimer0_etc[0] i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 58 n3 gpio flexpwm0 x[1] a0: siul_gpio[60] a1: flexpwm0_x[1] a2: _ a3: _ i: lin2_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io n4 gpio flexpwm0 b[2] a0: siul_gpio[100] a1: flexpwm0_b[2] a2: _ a3: _ i: _ i: etimer0_etc[5] i: _ ? disabled gp slow/ medium vdd_hv_io n20 gpio dramc dqs[1] a0: siul_gpio[191] a1: dramc_dqs[1] a2: ebi_ad25 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n21 gpio dramc dm[1] a0: siul_gpio[193] a1: dramc_dm[1] a2: ebi_ad27 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n22 gpio dramc d[13] a0: siul_gpio[187] a1: dramc_d[13] a2: ebi_ad21 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram n23 gpio dramc d[12] a0: siul_gpio[186] a1: dramc_d[12] a2: ebi_ad20 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram p1 gpio flexpwm0 b[0] a0: siul_gpio[59] a1: flexpwm0_b[0] a2: _ a3: _ i: _ i: etimer0_etc[1] i: _ ? disabled gp slow/ medium vdd_hv_io p2 gpio flexpwm0 b[1] a0: siul_gpio[62] a1: flexpwm0_b[1] a2: _ a3: _ i: _ i: etimer0_etc[3] i: _ ? disabled gp slow/ medium vdd_hv_io p3 gpio flexpwm0 a[2] a0: siul_gpio[99] a1: flexpwm0_a[2] a2: _ a3: _ i: _ i: etimer0_etc[4] i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 59 p4 gpio flexpwm0 a[3] a0: siul_gpio[102] a1: flexpwm0_a[3] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io p20 gpio dramc d[14] a0: siul_gpio[188] a1: dramc_d[14] a2: ebi_ad22 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram p21 gpio dramc d[15] a0: siul_gpio[189] a1: dramc_d[15] a2: ebi_ad23 a3: _ i: _ i: _ i: _ ? disabled dram dq vdd_hv_dram r1 gpio flexpwm0 x[2] a0: siul_gpio[98] a1: flexpwm0_x[2] a2: lin3_txd a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io r2 gpio flexpwm0 x[3] a0: siul_gpio[101] a1: flexpwm0_x[3] a2: _ a3: _ i: lin3_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io r3 gpio flexpwm0 a[1] a0: siul_gpio[80] a1: flexpwm0_a[1] a2: _ a3: _ i: _ i: etimer0_etc[2] i: _ ? disabled gp slow/ medium vdd_hv_io r21 gpio dramc add[3] a0: siul_gpio[161] a1: dramc_add[3] a2: ebi_add11 a3: ebi_tea i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram r22 gpio dramc cke a0: siul_gpio[147] a1: dramc_cke a2: ebi_oe a3: flexpwm0_a[0] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram t1 gpio flexpwm0 b[3] a0: siul_gpio[103] a1: flexpwm0_b[3] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 60 t2 gpio flexpwm1 a[0] a0: siul_gpio[117] a1: flexpwm1_a[0] a2: _ a3: can2_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io t3 gpio flexpwm1 a[1] a0: siul_gpio[120] a1: flexpwm1_a[1] a2: _ a3: can3_txd i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io t20 gpio dramc add[8] a0: siul_gpio[166] a1: dramc_add[8] a2: ebi_ad0 a3: ebi_add16 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram t21 gpio dramc add[9] a0: siul_gpio[167] a1: dramc_add[9] a2: ebi_ad1 a3: ebi_add17 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram t22 gpio dramc add[1] a0: siul_gpio[159] a1: dramc_add[1] a2: ebi_add9 a3: ebi_cs3 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram u1 gpio flexpwm1 b[0] a0: siul_gpio[118] a1: flexpwm1_b[0] a2: _ a3: _ i: can2_rxd i: can3_rxd i: _ ? disabled gp slow/ medium vdd_hv_io u2 gpio flexpwm1 b[1] a0: siul_gpio[121] a1: flexpwm1_b[1] a2: _ a3: _ i: can3_rxd i: can2_rxd i: _ ? disabled gp slow/ medium vdd_hv_io u3 gpio flexpwm1 a[2] a0: siul_gpio[123] a1: flexpwm1_a[2] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io u4 gpio dspi2 sck a0: siul_gpio[11] a1: dspi2_sck a2: _ a3: _ i: can3_rxd i: _ i: siul_eirq[10] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 61 u20 gpio dramc add[6] a0: siul_gpio[164] a1: dramc_add[6] a2: ebi_add14 a3: flexpwm1_a[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram u21 gpio dramc add[12] a0: siul_gpio[170] a1: dramc_add[12] a2: ebi_ad4 a3: ebi_add20 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram u23 gpio dramc add[0] a0: siul_gpio[158] a1: dramc_add[0] a2: ebi_add8 a3: ebi_cs2 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram v3 gpio flexpwm1 b[2] a0: siul_gpio[124] a1: flexpwm1_b[2] a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io v4 gpio dspi1 cs2 a0: siul_gpio[56] a1: dspi1_cs2 a2: _ a3: dspi0_cs5 i: flexpwm0_fault[3] i: lin2_rxd i: _ ? disabled gp slow/ medium vdd_hv_io v20 gpio lin0 txd a0: siul_gpio[18] a1: lin0_txd a2: i2c0_clock a3: sscm_debug[2] i: _ i: _ i: siul_eirq[17] ? disabled gp slow/ medium vdd_hv_io v21 gpio dramc add[13] a0: siul_gpio[171] a1: dramc_add[13] a2: ebi_ad5 a3: ebi_add21 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram v23 gpio dramc add[2] a0: siul_gpio[160] a1: dramc_add[2] a2: ebi_add10 a3: ebi_ta i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram w3 gpio dspi0 cs3 a0: siul_gpio[53] a1: dspi0_cs3 a2: i2c2_clock a3: _ i: flexpwm0_fault[2] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 62 w20 gpio lin0 rxd a0: siul_gpio[19] a1: _ a2: i2c0_data a3: sscm_debug[3] i: lin0_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io w21 gpio dramc add[14] a0: siul_gpio[172] a1: dramc_add[14] a2: ebi_ad6 a3: ebi_add22 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram w22 gpio dramc add[7] a0: siul_gpio[165] a1: dramc_add[7] a2: ebi_add15 a3: flexpwm1_b[2] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram w23 gpio dramc add[4] a0: siul_gpio[162] a1: dramc_add[4] a2: ebi_add12 a3: ebi_ale i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram y3 gpio dspi0 cs2 a0: siul_gpio[54] a1: dspi0_cs2 a2: i2c2_data a3: _ i: flexpwm0_fault[1] i: _ i: _ ? disabled gp slow/ medium vdd_hv_io y5 gpio flexpwm1 x[0] a0: siul_gpio[116] a1: flexpwm1_x[0] a2: etimer2_etc[0] a3: dspi0_cs1 i: ctu0_ext_in i: ctu1_ext_in i: _ ? disabled gp slow/ medium vdd_hv_io y6 ana adc3 an[0] ? siul_gpi[229] an: adc3_an[0] ? analog vdd_hv_adr23 y7 ana adc2_adc3 an[11] ? siul_gpi[225] an: adc2_adc3_an[11] ? analog shared vdd_hv_adr23 y8 ana adc2_adc3 an[14] ? siul_gpi[228] an: adc2_adc3_an[14] ? analog shared vdd_hv_adr23 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 63 y9 gpio etimer1 etc[1] a0: siul_gpio[45] a1: etimer1_etc[1] a2: _ a3: _ i: ctu0_ext_in i: flexpwm0_ext_sync i: ctu1_ext_in ? disabled gp slow/ medium vdd_hv_io y10 gpio etimer1 etc[2] a0: siul_gpio[46] a1: etimer1_etc[2] a2: ctu0_ext_tgr a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io y11 gpio etimer1 etc[3] a0: siul_gpio[92] a1: etimer1_etc[3] a2: _ a3: _ i: ctu1_ext_in i: mc_rgm_fab i: siul_eirq[30] ? pulldown gp slow/ medium vdd_hv_io y14 ana adc0_adc1 an[11] ? siul_gpi[25] an: adc0_adc1_an[11] ? analog shared vdd_hv_adr0 y15 gpio etimer1 etc[5] a0: siul_gpio[78] a1: etimer1_etc[5] a2: _ a3: _ i: _ i: _ i: siul_eirq[26] ? disabled gp slow/ medium vdd_hv_io y16 gpio etimer1 etc[4] a0: siul_gpio[93] a1: etimer1_etc[4] a2: ctu1_ext_tgr a3: _ i: _ i: _ i: siul_eirq[31] ? disabled gp slow/ medium vdd_hv_io y17 ana adc1 an[8] ? siul_gpi[74] an: adc1_an[8] ? analog vdd_hv_adr1 y18 ana adc1 an[6] ? siul_gpi[76] an: adc1_an[6] ? analog vdd_hv_adr1 y21 gpio dramc add[15] a0: siul_gpio[173] a1: dramc_add[15] a2: ebi_ad7 a3: ebi_add23 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 64 y22 gpio dramc add[11] a0: siul_gpio[169] a1: dramc_add[11] a2: ebi_ad3 a3: ebi_add19 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram y23 gpio dramc add[5] a0: siul_gpio[163] a1: dramc_add[5] a2: ebi_add13 a3: flexpwm1_b[1] i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram aa4 gpio dspi1 cs3 a0: siul_gpio[55] a1: dspi1_cs3 a2: lin2_txd a3: dspi0_cs4 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io aa5 gpio flexpwm1 x[1] a0: siul_gpio[119] a1: flexpwm1_x[1] a2: etimer2_etc[1] a3: dspi0_cs4 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io aa6 ana adc3 an[1] ? siul_gpi[230] an: adc3_an[1] ? analog vdd_hv_adr23 aa7 ana adc2_adc3 an[12] ? siul_gpi[226] an: adc2_adc3_an[12] ? analog shared vdd_hv_adr23 aa8 ana adc2 an[0] ? siul_gpi[221] an: adc2_an[0] ? analog vdd_hv_adr23 aa11 ana adc0 an[2] ? siul_gpi[33] an: adc0_an[2] ? analog vdd_hv_adr0 aa12 ana adc0 an[5] ? siul_gpi[66] an: adc0_an[5] ? analog vdd_hv_adr0 aa13 ana adc0 an[8] ? siul_gpi[69] an: adc0_an[8] ? analog vdd_hv_adr0 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 65 aa14 ana adc0_adc1 an[12] ? siul_gpi[26] an: adc0_adc1_an[12] ? analog shared vdd_hv_adr0 aa15 ana adc1 an[0] ? siul_gpi[29] lin1_rxd an: adc1_an[0] ? analog vdd_hv_adr1 aa16 ana adc1 an[2] ? siul_gpi[31] siul_eirq[20] an: adc1_an[2] ? analog vdd_hv_adr1 aa17 ana adc1 an[5] ? siul_gpi[64] an: adc1_an[5] ? analog vdd_hv_adr1 aa18 ana adc1 an[7] ? siul_gpi[73] an: adc1_an[7] ? analog vdd_hv_adr1 aa19 gpio tdi a0: siul_gpio[21] a1: _ a2: _ a3: _ i: jtagc_tdi i: _ i: _ ? pullup gp slow/ medium vdd_hv_io aa20 gpio etimer1 etc[0] a0: siul_gpio[4] a1: etimer1_etc[0] a2: _ a3: _ i: _ i: _ i: siul_eirq[4] ? disabled gp slow/ medium vdd_hv_io aa22 gpio lin1 txd a0: siul_gpio[94] a1: lin1_txd a2: i2c1_clock a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io aa23 gpio dramc add[10] a0: siul_gpio[168] a1: dramc_add[10] a2: ebi_ad2 a3: ebi_add18 i: _ i: _ i: _ ? disabled dram acc vdd_hv_dram ab3 gpio dspi2 sout a0: siul_gpio[12] a1: dspi2_sout a2: _ a3: _ i: _ i: _ i: siul_eirq[11] ? disabled gp slow/ medium vdd_hv_io table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 66 ab4 gpio flexpwm1 x[2] a0: siul_gpio[122] a1: flexpwm1_x[2] a2: etimer2_etc[2] a3: dspi0_cs5 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ab5 gpio flexpwm1 x[3] a0: siul_gpio[125] a1: flexpwm1_x[3] a2: etimer2_etc[3] a3: dspi0_cs6 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ab6 ana adc3 an[2] ? siul_gpi[231] an: adc3_an[2] ? analog vdd_hv_adr23 ab7 ana adc2_adc3 an[13] ? siul_gpi[227] an: adc2_adc3_an[13] ? analog shared vdd_hv_adr23 ab8 ana adc2 an[1] ? siul_gpi[222] an: adc2_an[1] ? analog vdd_hv_adr23 ab9 ana adc2 an[2] ? siul_gpi[223] an: adc2_an[2] ? analog vdd_hv_adr23 ab10 ana adc0 an[0] ? siul_gpi[23] lin0_rxd an: adc0_an[0] ? analog vdd_hv_adr0 ab11 ana adc0 an[4] ? siul_gpi[70] an: adc0_an[4] ? analog vdd_hv_adr0 ab12 ana adc0 an[6] ? siul_gpi[71] an: adc0_an[6] ? analog vdd_hv_adr0 ab13 ana adc0 an[7] ? siul_gpi[68] an: adc0_an[7] ? analog vdd_hv_adr0 ab14 ana adc0_adc1 an[13] ? siul_gpi[27] an: adc0_adc1_an[13] ? analog shared vdd_hv_adr0 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
package pinouts and signal descriptions MPC5675K microcontroller data sheet, rev. 7 freescale semiconductor 67 ab15 ana adc1 an[1] ? siul_gpi[30] etimer0_etc[4] siul_eirq[19] an: adc1_an[1] ? analog vdd_hv_adr1 ab16 ana adc1 an[3] ? siul_gpi[32] an: adc1_an[3] ? analog vdd_hv_adr1 ab17 ana adc1 an[4] ? siul_gpi[75] an: adc1_an[4] ? analog vdd_hv_adr1 ab18 gpio tdo a0: siul_gpio[20] a1: jtagc_tdo a2: _ a3: _ i: _ i: _ i: _ ? disabled gp slow/ fast vdd_hv_io ab21 gpio lin1 rxd a0: siul_gpio[95] a1: _ a2: i2c1_data a3: _ i: lin1_rxd i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ac3 gpio dspi2 sin a0: siul_gpio[13] a1: _ a2: _ a3: _ i: dspi2_sin i: flexpwm0_fault[0] i: siul_eirq[12] ? disabled gp slow/ medium vdd_hv_io ac4 gpio flexpwm1 a[3] a0: siul_gpio[126] a1: flexpwm1_a[3] a2: etimer2_etc[4] a3: dspi0_cs7 i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ac5 gpio flexpwm1 b[3] a0: siul_gpio[127] a1: flexpwm1_b[3] a2: etimer2_etc[5] a3: _ i: _ i: _ i: _ ? disabled gp slow/ medium vdd_hv_io ac6 ana adc3 an[3] ? siul_gpi[232] an: adc3_an[3] ? gp slow/ medium vdd_hv_adr23 ac9 ana adc2 an[3] ? siul_gpi[224] an: adc2_an[3] ? analog vdd_hv_adr23 table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
MPC5675K microcontroller data sheet, rev. 7 package pinouts and signal descriptions freescale semiconductor 68 ac10 ana adc0 an[1] ? siul_gpi[24] etimer0_etc[5] an: adc0_an[1] ? analog vdd_hv_adr0 ac11 ana adc0 an[3] ? siul_gpi[34] an: adc0_an[3] ? analog vdd_hv_adr0 ac14 ana adc0_adc1 an[14] ? siul_gpi[28] an: adc0_adc1_an[14] ? analog shared vdd_hv_adr0 end of 473 mapbga pin multiplexing table 1 do not connect pin directly to a power supply or ground. table 10. 473 mapbga pin multiplexing (continued) ball number ball type ball name alternate i/o additional inputs analog inputs weak pull during reset pad type power domain
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 69 3 electrical characteristics 3.1 introduction this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for this device. the ?symbol? column of th e electrical parameter and timings tables may cont ain an additional column containing ?sr?, ?cc?, ?p?, ?c?, ?t?, or ?d?. ? ?sr? identifies system requirements?conditions that mu st be provided to ensure normal device operation. an example is the input voltage of a voltage regulator. ? ?cc? identifies specifications that defi ne normal device operation. where availabl e, the letters ?p?, ?c?, ?t?, or ?d? replace the letter ?cc? and apply to these controller ch aracteristics. they specify how each characteristic is guaranteed. ? p: parameter is guaranteed by produc tion testing of each individual device. ? c: parameter is guaranteed by design characterization. measurements are taken from a statistically relevant sample size across process variations. ? t: parameter is guaranteed by design characterization on a small sample size from t ypical devices under typical conditions unless otherwise noted. all values are shown in the typical (?typ?) column are within this category. ? d: parameters are derived mainly from simulations. 3.2 absolute maximum ratings table 11. absolute maximum ratings 1 no. symbol parameter conditions min max unit 1v dd_hv_pmu sr voltage regulator supply voltage ? ?0.3 5.5 2 v 2v ss_hv_pmu sr voltage regulator supply ground ? ?0.1 0.1 v 3v dd_hv_io sr input/output supply voltage ? ?0.3 3.6 3,4 v 4v ss_hv_io sr input/output supply ground ? ?0.1 0.1 v 5v dd_hv_fla sr flash supply voltage ? ?0.3 3.6 3,4 v 6v ss_hv_fla sr flash supply ground ? ?0.1 0.1 v 7v dd_hv_osc sr crystal oscillator amplifier supply voltage ? ?0.3 3.6 3,4 v 8v ss_hv_osc sr crystal oscillator amplifier supply ground ? ?0.1 0.1 v 9v dd_hv_pdi sr pdi interface supply voltage ? ?0.3 3.6 3,4 v 10 v ss_hv_pdi sr pdi interface supply ground ? ?0.1 0.1 v 11 v dd_hv_dram 5 sr dram interface supply voltage ? ?0.3 3.6 3,4 v 12 v ss_hv_dram sr dram interface supply ground ? ?0.1 0.1 v 13 v dd_hv_adrx 6 sr adc x high reference voltage ? ?0.3 6.0 v 14 v ss_hv_adrx sr adc x low reference voltage ? ?0.1 0.1 v 15 v dd_hv_adv sr adc supply voltage ? ?0.3 3.6 3,4 v 16 v ss_hv_adv sr adc supply ground ? ?0.1 0.1 v 17 v dd_lv_cor sr core supply voltage digital logic ? ?0.3 1.32 7 v
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 70 3.3 recommended operating conditions 18 v ss_lv_cor sr core supply voltage ground digital logic ? ?0.1 0.1 v 19 v dd_lv_pll sr pll supply voltage ? ?0.3 1.32 v 20 v ss_lv_pll sr pll reference voltage ? ?0.1 0.1 v 21 tv dd sr slope characteristics on all v dd during power up ??25mv/s 22 v in sr voltage on any pin with respect to its supply rail v dd_hv_xxx relative to v dd_hv_xxx ?0.3 v dd_hv_xxx +0.3 8 v 23 i injpad sr injected input current on any pin during overload condition ? ?10 10 ma 24 i injpada sr injected input current on any analog pin during overload condition ? ?3 3 ma 25 i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 ma 26 t stg sr storage temperature ? ?55 9 150 c 27 t sdr sr maximum solder temperature 10 pb-free package snpb package ? ? ? 260 245 c 28 msl sr moisture sensitivity level 11 ??3? 1 functional operating conditions are given in the dc electric al characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 6.5 v for 10 hours cumulative time, 5.0 v + 10% for time remaining. 3 5.3 v for 10 hours cumulative over lifetime of device, 3.63 v for time remaining. 4 voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 as the v dd_hv_dram_vref supply should always be constrained by the v dd_hv_dram supply for example through a voltage divider network per the jedec spec ification, the maximum ratings for the v dd_hv_dram supply should be used for the v dd_hv_dram_vref reference as well. 6 all v dd_hv_adrx rails must be operated at the same supply voltage. 7 2.0 v for 10 hours cumulative time, 1.2 v + 10% for time remaining. 8 only when v dd_hv_xxx < 5.2 v. 9 if the ambient temperature is at or above the minimu m storage temperature and below the recommended minimum operating temperature, power may be applied to the device safely. however, functionality is not guaranteed and a power cycle must be administered if in internal regulation mode or an assertion of reset_sup_b must be administered if in external regulation mode once device enters into the recommended operating temperature range. 10 solder profile per cdf-aec-q100. 11 moisture sensitivity per jedec test method a112. table 12. recommended operating conditions 1 no. symbol parameter conditions min max unit 1v dd_hv_pmu sr voltage regulator supply voltage ? 3.0 5.5 v table 11. absolute maximum ratings 1 (continued) no. symbol parameter conditions min max unit
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 71 2v ss_hv_pmu sr voltage regulator supply ground ? 0 0 v 3v dd_hv_io sr input/output supply voltage ? 3.0 3.6 v 4v ss_hv_io sr input/output supply ground ? 0 0 v 5v dd_hv_fla sr flash supply voltage ? 3.0 3.6 v 6v ss_hv_fla sr flash supply ground ? 0 0 v 7v dd_hv_osc sr crystal oscillator amplifier supply voltage ? 3.0 3.6 v 8v ss_hv_osc sr crystal oscillator amplifier supply ground ? 0 0 v 9v dd_hv_pdi sr pdi interface supply voltage ? 1.62 3.6 v 10 v ss_hv_pdi sr pdi interface supply ground ? 0 0 v 11 v dd_hv_dram sr dram interface supply voltage ? 1.62 3.6 v 12 v ss_hv_dram sr dram interface supply ground ? 0 0 v 13 v dd_hv_adrx sr adc x high reference voltage ? 3.0 3.6 v alternate input voltage 4.5 5.5 14 v ss_hv_adrx sr adc x low reference voltage ? 0 0 v 15 v dd_hv_adv sr adc supply voltage ? 3.0 3.6 v 16 v ss_hv_adv sr adc supply ground ? 0 0 v 17 v dd_lv_cor sr core supply voltage digital logic 2 external vreg mode 1.14 1.32 v 17a cc internal vreg mode 1.14 1.32 v 18 v ss_lv_cor sr core supply voltage ground digital logic ? 0 0 v 19 v dd_lv_pll sr pll supply voltage 2 external vreg mode 1.14 1.32 v 19a cc internal vreg mode 1.14 1.32 v 20 v ss_lv_pll sr pll reference voltage ? 0 0 v 21 t a sr ambient temperature under bias 3,4 257 mapbga ?40 125 c 473 mapbga ?40 125 c 22 t j sr junction temperature under bias 4 257 mapbga ?40 150 c 473 mapbga ?40 150 1 these specifications are design targets and are subject to change per device characterization. 2 the jitter specifications for both plls holds true only up to 50 mv noise (peak to peak) on v dd_lv_cor and v dd_lv_pll . 3 see ta bl e 1 for available frequency and package options. 4 when determining if the operating temper ature specifications are met, either the ambient temperature or junction temperature specification can be used. it is not necessary that both specific ations be met at all times. however, it is critical that the junction temperature specification is no t exceeded under any condition. table 12. recommended operating conditions 1 (continued) no. symbol parameter conditions min max unit
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 72 3.4 thermal characteristics 3.4.1 general notes for specification s at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : t j =t a +(r ? ja p d ) eqn. 1 where: t a = ambient temperatur e for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient th ermal resistance is an industry st andard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the th ermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: table 13. thermal characteristics for package options 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. no. symbol parameter conditions value unit bga 257 bga 473 1r ? ja cc thermal resistance junction-to-ambient natural convection 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board ? 1s ? 40 ? 34 c/w 2r ? ja cc thermal resistance junction-to-ambient natural convection 2 four layer board ? 2s2p ? 22 ? 20 c/w 3r ? jma cc thermal resistance junction-to-moving-air ambient 2 @ 200 ft./min., single layer board ? 1s ? 32 ? 26 c/w 4r ? jma cc thermal resistance junction-to-moving-air ambient 2 @ 200 ft./min., four layer board ? 2s2p ? 18 ? 17 c/w 5r ? jb cc thermal resistance junction-to-board 3 3 junction-to-board thermal resistanc e determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. ? ? 10 ? 10 c/w 6r ? jc cc thermal resistance junction-to-case 4 4 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. ? ? 6 ? 6 c/w 7 ? jt cc junction-to-package-top natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. ? ? 2 ? 2c/w
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 73 r ? ja =r ? jc + r ? ca eqn. 2 where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) r ? jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of th e heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in th e application when heat sink s are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using equation 3 : t j =t t +( ? jt p d ) eqn. 3 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. see [6] to [10] in section 6, reference documents, for more information. 3.5 electromagnetic interference (emi) characteristics 3.5.1 test setup electromagnetic emission te sts are performed by tem cell [2] and via direct coupling [3] (150 ? ) measurements. electromagnetic immunity is measured by dpi [4] . see section 6, reference documents, for more information. 3.5.2 test parameters the following test parameters shall be used: table 14. emc test parameters method frequency range receiver bw step size 150 ? 1 mhz to 1000 mhz 1 mhz 500 khz tem
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 74 in case of only narrow band disturbances the maximum of the re sults will not change. in case of broadband signals the emission has to be below the limits. 3.6 electrostatic discharge (esd) characteristics electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size depends on the number of su pply pins in the device (3 parts ( n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. 3.7 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply over voltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.8 power management controller (pmc) electrical characteristics 3.8.1 pmc electrical specifications this section contains electrical characteristics for the pmc. table 15. esd ratings 1, 2 1 all esd testing is in conformity with cdf-aec-q100 st ress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. no. symbol parameter conditions class max value 3 3 data based on characterization resu lts, not tested in production. unit 1v esd(hbm) sr electrostatic discharge (human body model) t a =25c conforming to aec-q100-002 h1c 2000 v 2v esd(mm) sr electrostatic discharge (machine model) t a =25c conforming to aec-q100-003 m2 200 v 3v esd(cdm) sr electrostatic discharge (charged device model) t a =25c conforming to aec-q100-011 c3a 750 (corners) v 500 table 16. latch-up results no. symbol parameter conditions class 1 lu cc static latch-up class t a = 125 c conforming to jesd 78 ii level a
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 75 3.8.2 pmc board schematic and components figure 7 shows a sample application for the pmc. figure 7. pmu mandatory external components table 17. pmc electrical specifications no. symbol parameter min typ max unit 2 v dd_lv_cor cc nominal v rc regulated 1.2 v output v dd_hv_pmu ?1.28?v 3 porc cc por rising v dd 1.2 v ? por v dd variation ? por 1.2 v hysteresis ? porc ? 30% ? 0.7 porc 75 ? porc + 30% ? v v mv 4 lvdc cc nominal lvd 1.2 v ? lvd rising supply 1.2v after reset ? lvd rising supply 1.2v at reset ? lvd falling supply 1.2v after reset ? lvd falling supply 1.2v at reset ? 1.14 1.17 1.125 1.155 1.175 1.175 1.215 1.16 1.2 ? 1.21 1.26 1.195 1.245 v v v v v 5 hvdc cc nominal hvd 1.2 v ? hvd rising supply 1.2v after reset ? hvd rising supply 1.2v at reset ? hvd falling supply 1.2v after reset ? hvd falling supply 1.2v at reset ? 1.32 1.38 1.305 1.37 1.36 1.36 1.44 1.345 1.425 ? 1.4 1.5 1.385 1.48 v v v v 6 porreg cc por rising on v ddreg ? por v ddreg variation ? por v ddreg hysteresis ? porreg ? 30% ? 2.00 porreg 250 ? porreg +30% ? v v mv 7 lvdreg cc nominal rising lvd 3.3 v on v ddreg , v ddio , v ddflash , and v ddadc ? lvd 3.3 v variation at reset ? lvd 3.3 v variation after reset ? lvd 3.3 v hysteresis ? minimum slew rate ? maximum slew rate ? lvdreg ? 3.5% lvdreg ? 3% ? ? ? 2.865 lvdreg lvdreg 30 50 25 ? lvdreg +3.5% lvdreg +3% ? ? ? v v v mv mv/ms mv/s 8 lvdstepreg cc trimming step lvd 3.3 v ? 30 ? mv vdd_hv_pmu vss_hv_pmu vreg_ctrl vdd_lv_cor vss_lv_cor ca cb cd ce cl l r d q
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 76 3.9 supply current characteristics table 18. vrc smps recommended external devices reference designator part description part type nominal description ca ? capacitor 20 f, 20 v filter capacitor cb ? capacitor 0.1 f, 20 v filter capacitor cd ? capacitor 20 f, 20 v supply decoupling cap, esr < 50 m ? , as close to pmos source as possible ce ? capacitor 0.1 f, 16 v ceramic cl ? capacitor 20 f, 16 v buck capacitor, total esr < 100 m ? , as close to the coil as possible d ss8p3l schottky ? vishay low vf schottky diode l ? inductor 4 h, 1.5 a buck shielded coil low esr q fdc642p or sq2301es or si3443dv pmos 2 a, 10 v low threshold pmos v th < 1.5 v, r dson @4.5 v < 120 m ? , q g <16nc r ? resistor 50?100 k ? pullup for power pmos gate table 19. current consumption characteristics 1 no. symbol parameter cond itions min typ max unit 1i dd_lv cc maximum run i dd (incl. digital core logic and analog block of the lv rail) v dd_lv = 1.36 v, f core = 180 mhz, 1:2 mode, dpm, both cores executing emc test code, internal vreg mode, all caches enabled, code execution of core 0 from code flash 0, code execution of core 1 from code flash 1, fmpll_1 active at 120 mhz. ? 600 900 ma 2i dd_lv_pll cc maximum run i dd for each pll 2 v dd_lv_pll = 1.36 v, f vco running at maximum frequency. ?1.5 2 ma 3i dd_hv_fla 3 cc maximum run i dd flash v dd_hv_fla = 3.6 v, dpm, both cores executing emc test code, code execution of core 0 from code flash 0, code execution of core 1 from code flash 1. ?2030ma 4i dd_hv_osc cc maximum run i dd osc f osc 4 mhz to 40 mhz, v dd_hv_osc 3.6 v ?1 3ma 5i dd_hv_adv cc maximum run i dd for each adc 4 v dd_hv_adv =3.6v ? 2 4 ma 6i dd_hv_adr02 5 cc maximum reference i dd 6 adc0 powered on 7 ?? 2ma adc2 powered on ? ? 1.2 ma 7i dd_hv_adr13 5 cc maximum reference i dd 6 adc1 powered on ? ? 1.2 ma adc3 powered on ? ? 1.2 ma 8i dd_hv_adr0 8 cc maximum reference i dd adc0 powered on 7 ?? 2ma
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 77 3.10 temperature sensor electrical characteristics 3.11 main oscillator electrical characteristics the MPC5675K provides an oscillator/resonator driver. 9i dd_hv_adr1 8 cc maximum reference i dd adc1 powered on ? ? 1.2 ma 10 i dd_hv_adr23 8 cc maximum reference i dd 6 adc2 powered on ? ? 1.2 ma adc3 powered on ? ? 1.2 ma 1 applies to t j = ?40 c to 150 c. 2 total current on i dd_lv_pll needs to be multiplied with the number of active plls. 3 the current specified for i dd_hv_fla includes current consumed duri ng programming and erase operations. 4 total current on i dd_hv_adv needs to be multiplied with the number of active adcs. 5 257 mapbga only. 6 total current on i dd_hv_adrxx is the sum of both references if both adcs are powered on. 7 adc0 includes 0.7 ma dissipation for the temperature sensor (tsens). 8 473 mapbga only. table 20. temperature sensor electrical characteristics symbol parameter conditions min max unit 1 ? p accuracy t j = ?40 c to t a = 125 c ?10 10 c 2t s d minimum sampling period ? 4 ? s table 21. main oscillator electrical characteristics no. symbol parameter conditions 1 1 v dd = 3.0 v to 3.6 v, t j = ?40 to 150 c, unless otherwise specified. value unit min typ max 1f xoschs sr oscillator frequency ? 4.0 ? 40.0 mhz 2a t xoschssu cc oscillator start-up time f osc <16mhz ? 6 10 ms 2b f osc = 16 mhz to 40 mhz ? 2 4 3v ih sr input high level cmos schmitt trigger oscillator bypass mode 0.65 v dd ?v dd +0.4 v 4v il sr input low level cmos schmitt trigger oscillator bypass mode ?0.4 ? 0.35 v dd v table 19. current consumption characteristics 1 (continued) no. symbol parameter cond itions min typ max unit
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 78 3.12 fmpll electrical characteristics table 22. fmpll electrical characteristics no. symbol parameter conditions min typ max unit 1 f ref_crystal f ref_ext d fmpll reference frequency range 1, 2 1 considering operation with fmpll not bypassed. 2 pfd clock range is 4? 16 mhz. an appropriate pll input divi sion factor (idf) should be chosen to divide the reference frequency to this range. crystal reference 4 ? 120 mhz 2f pll_in d phase detector input frequency range (after pre-divider) ?4?16mhz 3f fmpllout d clock frequency range in normal mode see the fmpll chapter in the chip reference manual for more details on pll configuration. 16 ? 256 mhz 4f free p free running frequency measured using clock division (typically ? 16) 19 ? 60 mhz 5f sys d on-chip fmpll frequency 2 ? ? ? 180 mhz 6t cyc d system clock period ? ? ? 1 / f sys ns 7a f lorl f lorh d loss of reference frequency window 3 lower limit 1.6 ? 3.7 mhz 7b upper limit 24 ? 56 8f scm d self-clocked mode frequency 4,5 ? 20 ? 150 mhz 9t lock plock time stable oscillator (f pllin =4mhz), stable v dd ? ? 200 s 10 t lpll d fmpll lock time 6, 7 ? ? ? 200 ? s 11 t dc d duty cycle of reference ?20?80% 12a c jitter t clkout period jitter 8,9,10,11 peak-to-peak (clock edge to clock edge), f fmpllout maximum 12 ? ? 160 ps 12b long-term jitter (avg. over 2 ms interval), f fmpllout maximum ?? 6 ns 13 ? t pkjit t single period jitter (peak to peak) phi @ 16 mhz, input clock @ 4 mhz ??500 ps 14 ? t ltjit t long term jitter phi @ 16 mhz, input clock @ 4 mhz ?? 6 ns 15 f lck d frequency lock range ? ?4 ? +4 % f fmpllout 16 f ul d frequency un-lock range ? ?16 ? +16 % f fmpllout 17a f cs f ds d modulation depth center spread 0.25 ? 4 % f fmpllout 17b down spread ?0.5 ? ?8 18 f mod d modulation frequency 13 31 < ldf 14 <63 ldf > 63 ? ? (2240/ld f) 35 khz
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 79 3.13 16 mhz rc oscillator electrical characteristics 3.14 adc electrical characteristics the MPC5675K provides a 12-bit successive approximati on register (sar) analog-to-digital converter. 3 ?loss of reference frequency? window is the reference frequency range outside of which the fmpll is in self clocked mode. 4 self clocked mode frequency is the frequency that the fmpll ope rates at when the reference frequency falls outside the f lor window. 5 f vco is the frequency at the output of the vco; its range is 256?512 mhz. f scm is the self-clocked mode frequency (free running frequency); its range is 20?150 mhz. f sys =f vco ? odf 6 this value is determined by the crystal manufacturer and b oard design. for 4 mhz to 20 mhz crystals specified for this fmpll, load capacitors should not exceed these limits. 7 this specification applies to the period required for the fmpll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 8 this value is determined by the cr ystal manufacturer and board design. 9 jitter is the average deviation from the programmed freque ncy measured over the specified interval at maximum f fmpllout . measurements are made with the device powere d by filtered supplies and clocked by a stable external clock signal. noise injected into the fmpll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 10 proper pc board layout procedures must be followed to achieve specifications. 11 values are with frequency modulation disabled. if frequen cy modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 12 core operating at 180 mhz. 13 modulation depth is attenuated from depth setting when operating at mo dulation frequencies above 50 khz. 14 pll loop division factor (ldf). table 23. rc oscillator electrical characteristics no. symbol parameter conditions min typ max unit 1f rc cc rc oscillator frequency 25 c, 1.2 v trimmed ? 16 ? mhz 2 ? rcmvar cc frequency spread: the variation in output frequency from ptf 1 across temperature and supply voltage range 1 ptf = post trimming frequency: the frequency of the out put clock after trimming at typical supply voltage and temperature. ???5% 3 ? irctrim cc internal rc oscillator trimming step t a = 25 c ? 1.6 ? %
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 80 figure 8. adc characteristics and error definitions 3.14.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenua ting the noise present on the inpu t pin; further, it sources c harge during the sampling phase, when the analog si gnal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge sharing effects with the sampling capacitance: c s and c p2 being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq =1 / (f c ? c s ), where f c represents the conversion rate at the consider ed channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s +r f , the external circuit must be designed to respect equation 4 : eqn. 4 (2 ) (1) (3 ) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4089 40904091 4092 4093 4094 4095 1 lsb ideal =(vrefh-vrefl)/ 4096 = 3.3 v/ 4096 = 0.806 mv total unadjusted error tue = 6 lsb = 4.84 mv v a r s r f + r eq --------------------- ? 1 2 -- -lsb ?
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 81 equation 4 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 9. input equivalent circuit a second aspect involving the capacitance network shal l be considered. assuming the three capacitances c f , c p1 , and c p2 are initially charged at the source voltage v a (please see the equivalent circuit in figure 9 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch is closed). figure 10. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is: eqn. 5 r f c f r s r l r sw1 c p2 v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a c s v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ?
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 82 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 11. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 83 than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 table 24. adc conversion characteristics no. symbol parameter conditions 1 min typ max unit 1f ck sr adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_ck 2 frequency) ?3?60mhz 2f s sr sampling frequency ? ? ? 959 khz 3t adc_s d sample time 3 60 mhz 383 ? ? ns 4t adc_s _pmc c sample time of internal pmc channels. ? 717 ? ? ns 5t adc_e p evaluation time 4 60 mhz 600 ? ? ns 6c s 5 d adc input sampling capacitance ? ? ? 7.32 pf 7c p1 5 d adc input pin capacitance 1 ? ? ? 2.5 pf 8c p2 5 d adc input pin capacitance 2 ? ? ? 0.8 pf 9r sw1 5 d channel selection switch resistance v ref range=4.5to5.5v ? ? 1.0 k ? 10 v ref range=3.0to3.6v ? ? 1.2 k ? 11 r ad 5 d sample switching resistance ? ? ? 825 ? 12 i inj t current injection current injection on one adc input channel, different from the converted one. other parameters stay within specified limits as long as the adc supply stays within its specified limits due to the current injection. ?3 ? 3 ma 13 inl p integral non linearity ? ?3 ? 3 lsb 14 dnl p differential non linearity 6 ??1.0?2lsb v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 8192 c s ? ?
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 84 3.15 flash memory electrical characteristics 3.15.1 program/erase characteristics table 25 shows the code flash memory program and erase characteristics. 15 ofs t offset error ? ?4 ? 4 lsb 16 gne t gain error ? ?4 ? 4 lsb 17 tue 7 p total unadjusted error ? ?6 ? 6 lsb 18 tue 7 t total unadjusted error with current injection ? ?6 ? 6 lsb 19 snr t signal-to-noise ratio ? 69 ? ? db 20 thd t total harmonic distortion ? ?72 ? ? db 21 sinad t signal-to-noise and distortion ? 65 ? ? db 22 enob t effective number of bits ? 10.5 ? ? bits 1 v dd = 3.3 v, t j = ?40 to +150 c, unless otherwise specified and analog input voltage from v agnd to v aref . 2 ad_ck clock is always half of the adc module input clock defined via the auxiliary clock divider for the adc. 3 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capa citance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no ef fect on the conversion result. values for the sample clock t adc_s depend on programming. 4 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result register with the conversion result. 5 see figure 9 . 6 no missing codes. 7 when operating the MPC5675K in a switched mode power suppl y configuration, the specif ications for the adcs under worst case conditions can be upheld only through the use of averaging back-to-back samples. in the 257 package, 10 samples must be averaged when using adc 0, 2, or 3. in the 473 package, 5 samples must be averaged. for adc 1, due to its close proximity to the pmc, the tue spec must be increased to +/-10 counts, 10 samples of averaging must be used in both packages, and the vdd_hv_pmu supply must be below 3.6 v. better performance can be obtained with lower vdd_hv_pmu supplies and higher vdd_hv_adrx supplies. table 25. code flash memory program and erase electrical specifications no. symbol parameter min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 lifetime max 3 unit 1t dwprogram cc doubleword (64 bits) program time 4 ?18 50 500 s 2t 16kpperase cc 16 kb block pre-program and erase time ? 200 500 5000 ms 3t 32kpperase cc 32 kb block pre-program and erase time ? 300 600 5000 ms 4t 64kpperase cc 64 kb block pre-program and erase time ? 400 900 5000 ms 5t 128kpperase cc 128 kb block pre-program and erase time ? 600 1300 7500 ms table 24. adc conversion characteristics (continued) no. symbol parameter conditions 1 min typ max unit
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 85 table 26 shows the data flash memory program and erase characteristics. 2 initial max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supp ly values and operation at t j = 25 c. these values are verified at production test. 3 lifetime max program and erase times apply across the voltage, temperature, and cycling range of product life. these values are characterized, but not tested. 4 actual hardware programming times. this does not include software overhead. table 26. data flash memory program and erase electrical specifications no. symbol parameter min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supp ly values and operation at t j = 25 c. these values are verified at production test. lifetime max 3 3 lifetime max program and erase times apply across the voltage, temperature, and cycling range of product life. these values are characterized, but not tested. unit 1t dwprogram cc doubleword (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?30 70 300 s 2t 16kpperase cc 16 kb block pre-program and erase time ? 700 800 1500 ms table 27. flash memory module life no. symbol parameter condition value unit min typ 1 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typica l endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . max 1a p/e cc number of program/erase cycles per block for over the operating temperature range (t j ) 16 kb blocks 100,000 ? ? cycles 1b 32 kb and 64 kb blocks 10,000 100,000 ? cycles 1c 128 kb blocks 1,000 100,000 ? cycles 2 retention cc minimum data retention at 85 c average ambient temperature 2 2 ambient temperature averaged over duration of application, not to exceed product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? ? years blocks with 1,001?10,000 p/e cycles 10 ? ? years blocks with 10,001?100,000 p/e cycles 5 ? ? years
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 86 3.15.2 read access timing 3.15.3 write access timing 3.16 sram memory electrical characteristics table 28. code flash read access timing no. symbol parameter condition value unit max 1f read cc maximum frequency for flash reading (system clock frequency sys_clk) 4 wait states 90 mhz 2 3 wait states 60 mhz table 29. data flash read access timing no. symbol parameter condition value unit max 1f read cc maximum frequency for flash reading (system clock frequency sys_clk) 12 wait states 90 mhz 2 8 wait states 60 mhz table 30. code flash write access timing no. symbol parameter condition value unit max 1f write cc maximum frequency for flash writing (system clock frequency sys_clk) ? 90 mhz table 31. data flash write access timing no. symbol parameter condition value unit max 1f write cc maximum frequency for flash writing (system clock frequency sys_clk) ? 90 mhz table 32. system sram memory read/write access timing no. symbol parameter condition value unit max 1s read/write cc maximum frequency for system sram reading/writing (system clock frequency sys_clk) 1 wait state 90 mhz
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 87 3.17 gp pads specifications this section specifies the electrical characteristics of the gp pads . please refer to the tables in section 2.2, pin descriptions, for a cross reference between package pins and pad types. 3.17.1 gp pads dc specifications table 33 gives the dc electrical char acteristics at 3.3 v (3.0 v < v dd_hv_io <3.6v). table 33. gp pads dc electrical characteristics 1,2 1 these specifications are design targets and subject to change per device characterization. 2 the values provided in this table are not applicable for pdi and ebi/dram interface. no. symbol parameter conditions min max unit 1v il sr low level input voltage ? ?0.1 3 3 ?sr? parameter values must not exceed the absolute maximum ratings shown in ta b l e 1 1 . 0.35 v dd_hv_io v 2v ih sr high level input voltage ? 0.65 v dd_hv_io v dd_hv_io +0.1 3 v 3v hys cc schmitt trigger hysteresis ? 0.1 v dd_hv_io ?v 4v ol_s cc slow, low level output voltage i ol =1.5ma ? 0.5 v 5v oh_s cc slow, high level output voltage i oh =?1.5ma v dd_hv_io ?0.8 ? v 6v ol_m cc medium, low level output voltage i ol =2ma ? 0.5 v 7v oh_m cc medium, high level output voltage i oh =?2ma v dd_hv_io ?0.8 ? v 8v ol_f cc fast, high level output voltage i ol =11ma ? 0.5 v 9v oh_f cc fast, high level output voltage i oh = ?11 ma v dd_hv_io ?0.8 ? v 10 v ol_sym cc symmetric, high level output voltage i ol =5ma ? 0.5 v 11 v oh_sym cc symmetric, high level output voltage i oh =?5ma v dd_hv_io ?0.8 ? v 12 i pu cc equivalent pullup current v in =v il ?130 ? a v in =v ih ? ?10 13 i pd cc equivalent pulldown current v in =v il 10 ? a v in =v ih ? 130 14 i il cc input leakage current (all bidirectional ports) t a = ?40 to 125 c ?1a 15 i il cc input leakage current (all adc input-only ports) t a = ?40 to 125 c ?0.5a 16 v ilr sr reset , low level input voltage ? ?0.4 3 0.35 v dd_hv_io v 17 v ihr sr reset , high level input voltage ? 0.65 v dd_hv_io v dd_hv_io +0.4 3 v 18 v hysr cc reset , schmitt trigger hysteresis ? 0.1 v dd_hv_io ?v 19 v olr cc reset , low level output voltage i ol =2ma ? 0.5 v 20 i pd cc reset , equivalent pulldown current v in =v il 10 ? a v in =v ih ? 130 21 c in d input pad capacitance ? ? 3 pf
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 88 3.17.2 gp pads ac specifications 3.18 pdi pads specifications this section specifies the electrical characteristics of the pdi pads. please refer to the tables in section 2.2, pin descriptions, for a cross reference between package pins and pad types. pdi pads feature list: ? direction ? input ? output ? bidirectional ? driver ? push/pull/open drain ? configurable four drive strengths on fast driver pads ? configurable no slew-rate, slow slew-rate, and fast slew-rate on slow, medium, and slr driver pads ? vdd_hv_pdi note: all pads are not 5 v tolerant. pads are not capable of driving to or from voltages above their respective vdd_hv_pdi. in other words, you cannot connect a 3.3v external device to a pad table 34. gp pads ac electrical characteristics 1 1 the values provided in this table are not applicable for pdi and ebi/dram interface. no. pad tswitchon 1 (ns) rise/fall 2 (ns) 2 slope at rising/falling edge. frequency (mhz) current slew 3 (ma/ns) 3 data based on characterization resu lts, not tested in production. load drive (pf) min typ max min typ max min typ max min typ max 1 slow 3 ? 40 4 ? 40 ? ? 4 0.01 ? 2 25 3?406?50??20.01?2 50 3 ? 40 10 ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 14 ? 100 ? ? 2 0.01 ? 2 200 2 medium 1 ? 15 2 ? 12 ? ? 40 2.5 ? 7 25 1 ? 15 4 ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 8 ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 14 ? 70 ? ? 7 2.5 ? 7 200 3fast 1?61?4??723?4025 1?61.5?7??557?40 50 1?6 3?12??407?40 100 1?6 5?18??257?40 200 4symmetric1?8 1?5??503?25 25 5 pullup/down (3.6 v max) ?????7500?????? 50
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 89 supplied with 2.5 v. if a pad must be connected to a 3.3v device, its local vdd_hv_pdi must be 3.3 v. injection current is then handled by the in trinsic diodes from the pad transistors and by the esd diodes. ? vdd_hv_pdi range 1.8 v to 3.3 v, as specified in the following tables ? receiver ? selectable hysteresis input buffer ?cmos input buffer the electrical data provided in this section applies: ? to the pads listed in table 35 ? over the voltage range 1.62?3.6 v table 35. pdi i/o pads no. name voltage used for notes 1 pdi fast 1.62?3.6 v i/o enhanced operating voltage range fast slew-rate output with four selectable slew-rates. contains an input buffer and weak pullup/pulldown. 2pdi medium enhanced operating voltage range medium slew-rate output with four selectable slew-rates. contains an input buffer and weak pullup/pulldown. table 36. pdi pads dc electrical characteristics 1 1 over- and undershoots occurring due to impedance mismatch of the external driver and the transmission line at pdi pads in input mode can be allowed up to 0.7 v repeat edly throughout the product expected lifetime and will not cause any long term reliability issue. no. symbol parameter min max unit 1v dd_hv_pdi sr i/o supply voltage 1.62 3.6 v 2v ih_c cc cmos input buffer high voltage (hysteresis enabled) 0.65 v dd_hv_pdi v dd_hv_pdi +0.3 v 3v ih_c cc cmos input buffer high voltage (hysteresis disabled) 0.58 v dd_hv_pdi v dd_hv_pdi +0.3 v 4v il_c cc cmos input buffer low voltage (hysteresis enabled) v ss ? 0.3 0.35 v dd_hv_pdi v 5v il_c cc cmos input buffer low voltage (hysteresis disabled) v ss ? 0.3 0.42 v dd_hv_pdi v 6v hys_c cc cmos input buffer hysteresis 0.1 v dd_hv_pdi ?v 7i act_s cc selectable weak pullup/pulldown current 25 150 a 8v oh cc output high voltage 0.8 v dd_hv_pdi ?v 9v ol cc output low voltage ? 0.2 v dd_hv_pdi v table 37. drive current pad drive mode minimum i oh (ma) 1 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . pdi fast all 26.2 84.8 pdi medium all 19.2 52.1
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 90 3.19 dram pad specifications this section specifies the electrical characteristics of the dram pads . please refer to the tables in section 2.2, pin descriptions, for a cross reference between package pins and pad types. dram pads feature list: ? driver ? configurable to support lpddr half strength, lpddr full strength, ddr1, ddr2 half strength, ddr2 full strength, and sdr modes. ? vdd_hv_dram range of ? 1.8 v nominal ? 2.5 v nominal ? 3.3 v nominal ? receiver ? differential or pseudo-differential input buffer in all dram pads ? all inputs are tolerant up to their vdd_hv_dram absolute maximum rating ? data and strobe pads can be configured to support four signal termination options ? infinite/no termination ?50 ? ?75 ? table 38. pdi pads ac electrical characteristics no. name prop. delay (ns) l ? h/h ? l 1 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select minmaxminmax msb, lsb 1 pdi medium 0.8/0.7 -------- 1.1/1.08 5.5/4.5 1.02/1 ? 50 11 12/8.3 3.5/2.3 200 49/22 9.1/6 50 10 60/31 14/9.2 200 102/44 18/12 50 01 119/53 24/16 200 722/302 126/85 50 00 772/325 136/90 200 2 pdi fast 0.8/0.7 -------- 1.1/1.08 10/10 1.1/1.1 ? 50 11 15/15 2.6/2.6 200 15/15 2.4/2.4 50 10 22/22 5/5 200 24/24 5/5 50 01 33/33 8/8 200 66/66 16/16 50 00 84/84 21/21 200
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 91 ? 150 ? the electrical data provided in section 3.19, dram pad specifications, applies to the pads listed in table 39 . all three pad types can be configured to support sdr, ddr, dd r2 half and full strength, and lpddr half and full strength modes, according to table 40 . note 0.7 v overshoot/undershoot can be allowed to occur repeatedly throughout the product expected lifetime and will not cause any long term reliability issue. 3.19.1 dram pads electrical specifications (v dd_hv_dram = 3.3 v) table 39. dram pads name voltage used for notes 1 1 all pads can be configured to support lpddr half strength, lpddr full strength, ddr1, ddr2 half strength, ddr2 full strength, and sdr. dram acc 1.62 v?3.6 v i/o bidirectional ddr pad dram clk 1.62 v?3.6 v o output only differential clock driver pad dram dq 1.62 v?3.6 v i/o bidirectional ddr pad with integrated odt table 40. mode configuration for dram pads configuration 1 1 configuration is selected in the co rresponding pcr registers of the siul. mode 000 1.8 v lpddr half strength 001 1.8 v lpddr full strength 010 1.8 v ddr2 half strength 011 2.5 v ddr 100 not supported 101 not supported 110 1.8 v ddr2 full strength 111 sdr table 41. dram pads dc electrical specifications (v dd_hv_dram = 3.3 v) no. symbol parameter condition min max unit 1v dd_hv_dram sr i/o supply voltage ? 3.0 3.6 v 2 v dd_hv_dram_vref cc input reference voltage ?1.3 1.7v 3 v dd_hv_dram_vtt cc termination voltage 1 ?v dd_hv_dram_vref ? 0.05 v dd_hv_dram_vref +0.05 v 4v ih cc input high voltage ? v dd_hv_dram_vref + 0.20 ?v
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 92 3.19.2 dram pads electrical specification (v dd_hv_dram = 2.5 v) 5v il cc input low voltage ? v dd_hv_dram_vref ? 0.2 v 6v oh cc output high voltage ? v dd_hv_dram_vtt +0.8 ?v 7v ol cc output low voltage ? ? v dd_hv_dram_vtt ? 0.8 v 1 bga473: termination voltage can be supplied via package pins. bga257 termination voltage internally tied as the bga257 does not provide dram interface. disable odt. table 42. output drive current @ v dde = 3.3 v ( 10%) no. pad name drive mode minimum i oh (ma) 1 minimum i ol (ma) 2 1 dram acc 111 ?16 16 2 dram dq 3 dram clk 1 i oh is defined as the current sourced by the pad to drive the output to v oh . 2 i ol is defined as the current sunk by the pad to drive the output to v ol . table 43. dram pads ac electrical specifications (v dd_hv_dram = 3.3 v) no. pad name prop. delay (ns) l ? h/h ? l 1 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. output slew rate rise/fall (v/ns) drive load (pf) drive/slew rate select minmaxminmax msb, lsb 1 dram acc 1.4/1.4 2.4/2.4 3.1/2.5 5.6/5.4 5 111 1.7/1.7 2.7/2.7 0.9/1.1 1.7/2.0 20 111 2 dram dq 1.4/1.4 2.4/2.4 3.1/2.5 5.6/5.4 5 111 1.7/1.7 2.7/2.7 0.9/1.1 1.7/2.0 20 111 3 dram clk 1.4/1.4 2.4/2.4 3.1/2.5 5.7/5.7 5 111 1.6/1.6 2.6/2.6 1.1/1.3 2.3/2.3 20 111 table 44. dram pads dc electrical specifications (v dd_hv_dram = 2.5 v) no. symbol parameter condition min max unit 1v dd_hv_dram sr i/o supply voltage ? 2.3 2.7 v 2v dd_hv_dram_vref cc input reference voltage ? 0.49 v dd_hv_dram 0.51 v dd_hv_dram v 3v dd_hv_dram_vtt cc termination voltage 1 ?v dd_hv_dram_vref ? 0.04 v dd_hv_dram_vref +0.04 v table 41. dram pads dc electrical specifications (v dd_hv_dram = 3.3 v) (continued) no. symbol parameter condition min max unit
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 93 3.19.3 dram pads electrical specification (v dd_hv_dram = 1.8 v) 4v ih cc input high voltage ? v dd_hv_dram_vref +0.15 ?v 5v il cc input low voltage ? ? v dd_hv_dram_vref ?0.15 v 6v oh cc output high voltage ? v dd_hv_dram_vtt +0.81 ?v 7v ol cc output low voltage ? ? v dd_hv_dram_vtt ?0.81 v 1 473 mapbga: termination voltage can be supplied via package pins. 257 mapbga termination voltage internally tied as the 257 mapbga does not pr ovide dram interface. disable odt. table 45. output drive current @ v dde = 2.5 v ( 200 mv) pad name drive mode minimum i oh (ma) 1 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . dram acc 011 ?16.2 16.2 dram dq 011 dram clk 011 table 46. dram pads ac electrical specifications (v dd_hv_dram = 2.5 v) no. pad name prop. delay (ns) l ? h/h ? l 1 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb 1 dram acc 1.4/1.5 2.5/2.4 2.1/2.1 4.3/4.1 5 011 1.7/1.7 2.8/2.7 0.6/0.7 1.1/1.3 20 2 dram dq 1.4/1.5 2.5/2.4 2.1/2.1 4.3/4.1 5 011 1.7/1.7 2.8/2.7 0.6/0.7 1.1/1.3 20 3 dram clk 1.4/1.4 2.4/2.4 2.1/2.1 4.4/4.1 5 011 1.6/1.6 2.7/2.7 0.6/0.7 1.6/1.8 20 table 47. dram pads dc electrical specifications (v dd_hv_dram = 1.8 v) no. symbol parameter condition min max unit 1v dd_hv_dram sr i/o supply voltage ? 1.62 1.9 v table 44. dram pads dc electrical specifications (v dd_hv_dram = 2.5 v) (continued) no. symbol parameter condition min max unit
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 94 2v dd_hv_dram_vref cc input reference voltage ? 0.49 v dd_hv_dram 0.51 v dd_hv_dram v 3v dd_hv_dram_vtt cc termination voltage 1 ?v dd_hv_dram_vref ?0.04 v dd_hv_dram_vref +0.04 v 4v ih cc input high voltage ? v dd_hv_dram_vref + 0.125 ? v 5v il cc input low voltage ? ? v dd_hv_dram_vref ?0.125 v 6v oh cc output high voltage ? 1.42 ? v 7v ol cc output low voltage ? ? 0.28 v 1 bga473: termination voltage can be supplied via package pins . bga257 termination voltage internally tied as the bga257 does not provide dram interface. disable odt. table 48. output drive current @ v dde = 1.8 v ( 100 mv) no. pad name drive mode minimum i oh (ma) 1 1 i oh is defined as the current sourced by the pad to drive the output to v oh . minimum i ol (ma) 2 2 i ol is defined as the current sunk by the pad to drive the output to v ol . 1 dram acc 000 ?3.57 3.57 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 2 dram dq 000 ?3.57 3.57 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 3 dram clk 000 ?3.57 3.57 001 ?7.84 7.84 010 ?5.36 5.36 110 ?13.4 13.4 table 47. dram pads dc electrical specifications (v dd_hv_dram = 1.8 v) (continued) no. symbol parameter condition min max unit
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 95 table 49. dram pads ac electrical specifications (v dd_hv_dram = 1.8 v) no. pad name prop. delay (ns) l ? h/h ? l 1 1 l ? h signifies low-to-high propagation delay and h ? l signifies high-to-low propagation delay. rise/fall edge (ns) drive load (pf) drive/slew rate select min max min max msb, lsb 1 dram acc 1.4/1.4 2.4/2.4 0.6/1.0 2.7/2.6 5 000 1.7/1.7 2.8/2.7 0.2/0.4 0.5/0.6 20 1.4/1.5 2.4/2.5 1.1/1.1 3.0/2.7 5 001 1.7/1.7 2.8/2.8 0.4/0.4 0.7/0.7 20 1.4/1.5 2.4/2.4 1.0/1.1 2.9/2.7 5 010 1.7/1.7 2.8/2.7 0.3/0.4 0.6/0.7 20 1.4/1.5 2.5/2.5 1.5/1.1 3.1/2.6 5 110 1.7/1.8 2.8/2.8 0.4/0.4 0.7/0.6 20 2 dram dq 1.4/1.4 2.4/2.4 0.6/1.0 2.7/2.6 5 000 1.7/1.7 2.8/2.7 0. 2/0.4 0.5/0.6 20 1.4/1.5 2.4/2.5 1.1/1.1 3.0/2.7 5 001 1.7/1.7 2.8/2.8 0.4/0.4 0.7/0.7 20 1.4/1.5 2.4/2.4 1.0/1.1 2.9/2.7 5 010 1.7/1.7 2.8/2.7 0. 3/0.4 0.6/0.7 20 1.4/1.5 2.5/2.5 1. 5/1.1 3.1/2.6 5 110 1.7/1.8 2.8/2.8 0. 4/0.4 0.7/0.6 20 3 dram clk 1.4/1.4 2.4/2.4 0.4/0.6 2.7/2.7 5 000 1.6/1.6 2.7/2.7 0.7/0.9 1.8/3.4 20 1.4/1.4 2.4/2.4 1.1/1.1 3.0/2.8 5 001 1.7/1.7 2.7/2.7 0.3/0.4 1.0/1.1 20 1.4/1.4 2.4/2.4 0.9/1.1 3.0/2.8 5 010 1.6/1.6 2.7/2.7 0.3/0.4 0.9/1.0 20 1.4/1.4 2.5/2.5 1.5/1.2 3.2/2.6 5 110 1.7/1.7 2.7/2.7 0.4/0.4 1.1/1.2 20
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 96 3.20 reset characteristics 3.20.1 reset pin characteristics 3.20.2 reset _sup_b pin characteristics 3.21 reset sequence this section shows the duration for different reset sequences. it describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences depending on internal or external vreg mode. 3.21.1 reset sequence duration table 52 specifies the minimum and the maximum reset sequence dura tion for the five different reset sequences described in section 3.21.2, reset sequence description. table 50. reset pin characteristics no. symbol parameter conditions min max unit 1w frst sr reset pulse is sure to be filtered ? ? 70 ns 2w nfrst sr reset pulse is sure not to be filtered ? 400 ? ns table 51. reset_sup_b pin characteristics no. symbol parameter conditions min max unit 1w frst sr reset_sup_b pulse is sure to be filtered (there is no internal filter on this pin) ??0ns 2t rstsup sr reset_sup_b release by an external delay/monitor circuit after all supplies are stable ?0?ns table 52. reset sequences no. symbol parameter t reset unit min typ max 1 1 the maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of reset by an external reset generator. 1 t drb cc destructive reset sequence, bist enabled 60 65 70 ms 2 t dr cc destructive reset sequence, bist disabled 40 400 1000 s 3 t erlb cc external reset sequence long, bist enabled 60 65 70 ms 4 t frl cc functional reset sequence long 40 300 600 s 5 t frs cc functional reset sequence short 1 3 10 s
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 97 3.21.2 reset sequence description the figures in this section show the intern al states of the MPC5675K during the fi ve different reset sequences. the doted lines in the figures indicate the starting point and the end point for which the duration is specified in table 52 . the start point and end point conditions as well as the reset trigger mappi ng to the different reset sequences is specified in section 3.21.3, reset sequence trigger mapping. with the beginning of drun mode, the first instruction is fetche d and executed. at this point, application execution starts and the internal reset sequence is finished. the following figures show the internal states of the MPC5675K durin g the execution of the reset sequence and the possible states of the reset signal pin. note reset is a bidirectional pin. the voltage level on this pin can either be driven low by an external reset generator or by the MPC5675K internal reset circuitry. a high level on this pin can only be generated by an external pullup resistor which is strong enough to overdrive the weak internal pulldown resistor. the rising edge on reset in the following figures indicates the time when the de vice stops driving it low. the reset sequence durations given in table 52 are applicable only if the internal rese t sequence is not prolonged by an external reset generator keeping reset asserted low beyond the last phase3. figure 12. destructive reset sequence, bist enabled figure 13. destructive reset sequence, bist disabled phase0 phase1,2 phase3 phase1,2 phase3 drun bist reset sequence trigger reset sequence start condition reset establish flash device self mbist lbist application irc and pwr init te s t setup config flash init device config execution t drb, min < t reset < t drb, max phase0 phase1,2 phase3 drun reset sequence trigger reset sequence start condition reset establish flash device application irc and pwr init config execution t dr, min < t reset < t dr, max
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 98 figure 14. external reset sequence long, bist enabled figure 15. functional reset sequence long figure 16. functional reset sequence short the reset sequences shown in figure 15 and figure 16 are triggered by functional reset events. reset is driven low during these two reset sequences only if the corresponding functional re set source (which triggered the reset sequence) was enabled to drive reset low for the duration of the internal reset sequence. see the rgm_fbre register in the MPC5675K reference manual for more information. 3.21.3 reset sequence trigger mapping the following table shows the possible trigge r events for the different reset sequences , depending on the vreg mode (external or internal). it specifies the reset sequ ence start conditions as well as the reset sequence end indications that are the basis for the timing data provided in table 52 . phase1,2 phase3 phase1,2 phase3 drun bist reset sequence trigger reset sequence start condition reset flash device self mbist lbist application init te s t setup config flash init device config execution t erlb, min < t reset < t erlb, max phase1,2 phase3 drun reset sequence trigger reset sequence start condition reset application flash init device config execution t frl, min < t reset < t frl, max phase3 drun reset sequence trigger reset sequence start condition reset application execution t frs, min < t reset < t frs, max
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 99 table 53. reset sequence trigger?reset sequence reset sequence trigger vreg mode 1 1 vreg mode: i = internal vreg mode, e = external vreg mode. reset sequence start condition reset sequence end indication reset sequence destructive reset sequence, bist enabled 2 2 whether bist is executed or not depends on device conf iguration data stored in the shadow sector of the nvm. destructive reset sequence, bist disabled 2 external reset sequence long, bist enabled functional reset sequence long functional reset sequence short all active internal destructive reset sources (lvds or internal hvd during power-up and during operation) i section 3. 21.4.1, internal vreg mode release of reset 3 3 end of the internal reset sequence (as specified in table 52 ) can only be observed by release of reset if it is not held low externally beyond the end of the in ternal sequence which would prolong t he internal reset phase3 until reset is released externally. triggers cannot trigger cannot trigger cannot trigger e section 3. 21.4.2, external vreg mode cannot trigger cannot trigger cannot trigger assertion of reset_sup 4 4 in external vreg mode only. assertion of reset 5 5 the assertion of reset can only trigger a reset sequenc e if the device was running (reset released) before. reset does not gate a destructive reset sequence, bist enabled or a destructive reset sequence, bist disabled . however, it can prolong these sequences if reset is held low externally beyond the end of the internal sequence (beyond phase3). i/e section 3. 21.4.3, external reset via reset cannot trigger triggers 6 6 if reset is configured for long reset (default) and if bist is enabled via device configuration data stored in the shadow sector of the nvm. triggers 7 7 if reset is configured for long reset (default) and if bist is disabled via device configuration data stored in the shadow sector of the nvm. triggers 8 all internal functional reset sources configured for long reset i/e sequence starts with internal reset trigger release of reset 9 cannot trigger cannot trigger triggers cannot trigger all internal functional reset sources configured for short reset i/e cannot trigger cannot trigger cannot trigger triggers
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 100 3.21.4 reset sequence?start condition the impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a ve ry slow slew rate compared to the overall reset sequence duration. 3.21.4.1 internal vreg mode figure 17 shows the voltage threshold that determines the start of the destructive reset sequence, bist enabled and the start for the destructive reset sequence, bist disabled . the last voltage rail crossing the levels shown in figure 17 determines the start of the reset times specified in table 52 . figure 17. reset sequence start in internal vreg mode 3.21.4.2 external vreg mode figure 18 and figure 19 show the voltage thresholds that determine the st art of the destructive reset sequence, bist enabled and the start for the destructive reset sequence, bist disabled. note reset_sup must not be released unless v dd_lv_ xxx is within its valid range of operation. reset_sup input circuitry needs a valid v dd_hv_io rail in order to detect a high level on reset_sup . 8 if reset is configured for short reset. 9 internal reset sequence can only be observed by state of reset if bidirectional reset functionality is enabled for the functional reset source which triggered the reset sequence. table 54. voltage thresholds variable name value v min lvdreg ? 3.5% v max lvdreg + 3.5% supply rail vdd_hv_pmu vdd_hv_io vdd_hv_flash vdd_hv_adv v max supply rail v min v t t reset, min starts here t reset, max starts here
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 101 figure 18. external vreg mode, reset_sup rises after v dd_hv_ xxx are stable figure 19. external vreg mode, reset_sup rises with v dd_hv_ xxx note in case reset_sup has reached a valid high level before v dd_hv_io is stable, the reset sequence will start as documented in figure 19 as the reset_sup input circuitry needs a valid v dd_hv_io rail in order to detect a high level on reset_sup . vdd_hv_pmu v t 0.8 vdd_hv_io reset_sup v t t reset, min starts here t reset, max starts here vdd_hv_io vdd_hv_flash vdd_hv_adv 0.2 vdd_hv_io min vdd_hv_xxx min vdd_lv_xxx t rstsup vdd_lv_core vdd_lv_pll vdd_hv_pmu v t lvdreg + 3.5% reset_sup v t t reset, min starts here t reset, max starts here vdd_hv_io vdd_hv_flash vdd_hv_adv lvdreg ? 3.5%
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 102 3.21.4.3 external reset via reset figure 20 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of reset as specified in table 53 . figure 20. reset seque nce start via reset assertion 3.21.5 external watchdog window if the application design requires the use of an external watchdog the data provided in section 3.21, reset sequence can be used to determine the correct positioning of the trigger window for the external watchdog. figure 21 shows the relationships between the minimum and the maximum duration of a given reset sequen ce and the position of an external watchdog trigger window. figure 21. reset sequence?external watchdog trigger window position 3.22 peripheral timing characteristics 3.22.1 sdram (ddr) the MPC5675K memory controller supports three types of ddr devices: ? ddr-1 (sstl_2 class ii interface) ? ddr-2 (sstl_18 interface) ? lpddr/mobile-ddr (1.8 v i/o supply voltage) 0.65 vdd_hv_io reset_sup v t t reset, min starts here t reset, max starts here 0.352 vdd_hv_io internal reset sequence start condition (signal or voltage rail) earliest application start latest application start application time required to prepare watchdog trigger t wdstart, min t wdstart, max t reset, min t reset, max watchdog needs to be triggered within this window external watchdog window open external watchdog window open external watchdog window closed basic application init basic application init application running application running watchdog trigger external watchdog window closed
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 103 jedec standards define the minimum set of requirements for compliant memory devices: ? jedec standard, ddr2 sdram specification, jesd79-2c, may 2006 ? jedec standard, double data rate (ddr) sdram specification, jesd79e, may 2005 ? jedec standard, low power double data rate (lpddr) sdram specification, jesd79-4, may 2006 the MPC5675K supports the configuration of tw o output drive strengths for ddr2 and lpddr: ? full drive strength ? half drive strength (intended for lighter loads or point-to-point environments) the MPC5675K memory controller supports dynamic on-die termination in the host device and in the ddr2 memory device. this section includes ac specificat ions for all ddr sdram pins. the dc parameters are specified in the section 3.19, dram pad specifications. 3.22.1.1 ddr and ddr2 sdram ac timing specifications figure 22 shows the ddr sdram write timing. table 55. ddr and ddr2 (ddr2-4 00) sdram timing specifications at recommended operatin g conditions with v dd_mem_io of ? 5% no. symbol parameter min max unit 1t ck cc clock cycle time, cl = x ?90mhz 2v ix-ac cc mck ac differential crosspoint voltage 1 1 measured with clock pin loaded with differential 100 ? termination resistor. v dd_mem_io 0.5 ?0.1 v dd_mem_io 0.5 +0.1 v 3t ch cc ck high pulse width 1, 2 2 all transitions measured at mid-supply ( v dd_mem_io /2). 0.47 0.53 t ck 4t cl cc ck low pulse width 1, 2 0.47 0.53 t ck 5t dqss cc skew between mck and dqs transitions 2, 3 3 measured with all outputs e xcept the clock loaded with 50 ? termination resistor to v dd_mem_io /2. ? 0.25 0.25 t ck 6t os(base) cc address and control output setup time relative to mck rising edge 2, 3 (t ck /2 ? 750) ps 7t oh(base) cc address and control output hold time relative to mck rising edge 2, 3 (t ck /2 ? 750) ? ps 8t ds1(base) cc dq and dm output setup time relative to dqs 2, 3 (t ck /4 ? 500) ? ps 9t dh1(base) cc dq and dm output hold time relative to dqs 2, 3 (t ck /4 ? 500) ? ps 10 t dqsq cc dqs-dq skew for dqs and associated dq inputs 2 ?(t ck /4 ? 600) (t ck /4?600) ps
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 104 figure 22. ddr write timing figure 23 and figure 24 show the ddr sdram read timing. figure 23. ddr read timing, dq vs. dqs figure 24. ddr read timing, dqsen figure 25 provides the ac test load for the ddr bus. mck t ch t cl dqs t dqss dq, dm (out) t ds t dh t ck dqs (in) any dq (in) t dqsq t dqsq mck dqs (in) t os t oh command address read t dqsen (min) t dqsen
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 105 figure 25. ddr ac test load 3.22.2 ieee 1149.1 (jtag) interface timing 3.22.2.1 standard interface timing 3.22.2.2 interface timing for full cycle mode table 56. jtag pin ac electrical characteristics no. symbol parameter conditions min max unit 1t jcyc d tck cycle time 1 1 f tck =1/t tck . f tck needs to be smaller than the system clock (sys_clk). ?60?ns 2t jdc d tck clock pulse width (measured at v dde /2) ? 40 60 % 3t tckrise d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis d tms, tdi data setup time ? 12 ? ns 5t tmsh, t tdih d tms, tdi data hold time ? 6 ? ns 6t tdov d tck low to tdo data valid ? ? 18 ns 7t tdoi d tck low to tdo data invalid ? 6 ? ns 8t tdohz d tck low to tdo high impedance ? ? 18 ns 9t bsdv d tck falling edge to output valid (bsr) ? ? 14 ns 10 t bsdvz d tck falling edge to output valid out of high impedance (bsr) ??15ns 11 t bsdhz d tck falling edge to output high impedance (bsr) ? ? 10 ns 12 t bsdst d boundary scan input valid to tck rising edge ? 15 ? ns 13 t bsdht d tck rising edge to boundary scan input invalid ? 2 ? ns table 57. jtag pin full cycle mode ac electrical characteristics no. symbol parameter conditions min max unit 1t jcyc d tck cycle time 1 ?40?ns 2t jdc d tck clock pulse width (measured at v dde /2) ? 40 60 % 3t tckrise d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis d tms, tdi data setup time ? 12 ? ns 5t tmsh, t tdih d tms, tdi data hold time ? 6 ? ns 6t tdov d tck low to tdo data valid ? ? 18 ns 7t tdoi d tck low to tdo data invalid ? 6 ? ns output z 0 =50 ? r l = 50 ? v dd_mem_io /2
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 106 figure 26. jtag test clock input timing figure 27. jtag test access port timing 1 f tck =1/t tck . f tck needs to be smaller than the system clock (sys_clk). this frequency is valid only in special modes where tdo is sampled at the next falling edge for co re0/1 nexus taps and hence full cycle is given to tdo for settling before it is sampled. tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 107 figure 28. jtag boundary scan timing 3.22.3 nexus timing table 58. nexus debug port timing div mode = 2 1 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. rise/fall time for nexus signals can be derived from fast gpio pad specification section. no. symbol parameter conditions min max unit 1t mcko cc mcko cycle time ? 16.67 ? ns 2t mdc cc mcko duty cycle 2 2 jitter/tolerance for mcko clock is derived from pll. please see pll section for jitter specification. ?5050% 3t mdov cc mcko low to mdo, mseo , evto data valid 3 3 mdo, mseo , and evto data is held valid until next mcko low cycle in sdr m ode. for ddr mode, this timing is same for both mcko edges. ? ?1.67 3.34 ns 4t evtipw cc evti pulse width. captured on jtag tck. ? 4.0 ? t jcyc 5t pw cc mdo, mseo ,evto pulse width in sdr mode ? 1 ? t mcko tck output signals input signals output signals 11 12 13 14 15
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 108 figure 29. nexus sdr (even divisor) timing figure 30. nexus sdr ou tput timing for div=3 table 59. nexus debug port timing divide by 3 sdr mode 1 1 mdo, mseo , and evto data is held valid until next mcko low cycle in sdr mode. rise/fall time for nexus signals can be derived from fast gpio pad specification section. no. symbol parameter conditions min max unit 1t mcko cc mcko cycle time ? 16.67 ? ns 2t mdc cc mcko duty cycle 2 2 jitter/tolerance for mcko clock is derived from pll. please see pll section for jitter specification. ?3366% 3t mdov cc mcko low to mdo, mseo , evto data valid ? ?1.67 3.34 ns 4t evtipw cc evti pulse width. captured on jtag tck. ? 4.0 ? t jcyc 5t pw cc mdo, mseo ,evto pulse width in sdr mode ? 1 ? t mcko 1 2 mcko mdo mseo evto output data valid 3 evti 4 5 1 2 mcko mdo mseo evto output data valid 3 evti 4 5
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 109 figure 31. nexus ddr mode timing 3.22.4 external interrupt timing (irq pins) table 60. nexus debug port timing divide by 4 ddr mode 1 1 all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal.rise/fall time for nexus signals can be derived from fast gpio pad specification section. no. symbol parameter conditions min max unit 1t mcko cc mcko cycle time ? 22.22 ? ns 2t mdc cc mcko duty cycle 2 2 jitter/tolerance for mcko clock is derived from pll. please see pll section for jitter specification. ?5050% 3t mdov cc mcko low to mdo, mseo , evto data valid 3 3 mdo, mseo , and evto data is held valid for half of time period. using this time period, data valid window for these signals is between 0.2 t mcko to 0.4 t mcko starting from each mcko edge. ? ?2.23 4.45 ns 4t evtipw cc evti pulse width ? 4.0 ? t jcyc 5t pw cc mdo, mseo ,evto pulse width in ddr mode ? 0.5 ? t mcko table 61. external interrupt timing (nmi irq) no. symbol parameter conditions min max unit 1t ipwl sr irq pulse width low ? 3 ? t cyc 2t ipwh sr irq pulse width high ? 3 ? t cyc 3t icyc sr irq edge to edge time 1 1 applies when irq pins are configured for ri sing edge or falling edge events, but not both. ?6?t cyc table 62. external interrupt timing (gpio irq) no. symbol parameter conditions min max unit 1t ipwl sr irq pulse width low ? 3 ? t cyc 2t ipwh sr irq pulse width high ? 3 ? t cyc 1 2 mcko mdo mseo output data valid 3 5
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 110 figure 32. external interrupt timing 3.22.5 flexcan timing 3.22.6 dspi timing 3t icyc sr irq edge to edge time 1 ?6?t cyc 1 applies when irq pins are configured for ri sing edge or falling edge events, but not both. table 63. flexcan timing no. symbol parameter co nditions min max unit 1f can_tx cc flexcan design target transmit data rate ? 10 ? mbit/s 2f can_rx cc flexcan design target receive data rate ? 10 ? mbit/s table 64. dspi timing no. symbol parameter conditions min max unit 1t sck cc dspi cycle time master (mtfe = 0) 62 ? ns slave (mtfe = 0) 62 ? slave receive only mode 1 16 ? 2t csc cc pcs to sck delay ? 16 ? ns 3t asc cc after sck delay ? 16 ? ns 4t sdc cc sck duty cycle ? 0.4 t sck 0.6 t sck ns 5t a cc slave access time ss active to sout valid ? 40 ns table 62. external interrupt timing (gpio irq) (continued) no. symbol parameter conditions min max unit clkout irq 1 2 3
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 111 6t dis cc slave sout disable time ss inactive to sout high-z or invalid ? 10 ns 7t pcsc cc pcsx to pcss time ? 13 ? ns 8t pasc cc pcss to pcs x time ? 13 ? ns 9t sui cc data setup time for inputs master (mtfe = 0) 20 ? ns slave 2? master (mtfe = 1, cpha = 0) 5? master (mtfe = 1, cpha = 1) 20 ? 10 t hi cc data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? 11 t suo cc data valid (after sck edge) master (mtfe = 0) ? 4 ns slave ? 23 master (mtfe = 1, cpha = 0) ? 11 master (mtfe = 1, cpha = 1) ? 5 12 t ho cc data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ?2 ? 13 t dt cc delay after transfer (minimum cs negation time) continuous mode non-continuos mode 2 62 134 ? ? ns 1 slave receive only mode can operate at a maximum frequen cy of 60 mhz. note that in this mode, the dspi can receive data on sin, but no valid data is transmitted on sout. 2 in non-continuous mode, this value is always t sck dspi_ctar n [dt] dspi_ctar n [pdt]. the minimum permissible value of dt is 2 and the minimum permissibl e value of pdt is 1. see the dspi chapter of the MPC5675K reference manual for more information. table 64. dspi timing (continued) no. symbol parameter conditions min max unit
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 112 figure 33. dspi classic spi timing?master, cpha = 0 figure 34. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1)
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 113 figure 35. dspi classic spi timing?slave, cpha = 0 figure 36. dspi classic spi timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 114 figure 37. dspi modified transfer format timing?master, cpha = 0 figure 38. dspi modified transfer format timing?master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1)
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 115 figure 39. dspi modified transfer format timing?slave, cpha = 0 figure 40. dspi modified transfer format timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1)
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 116 figure 41. example of non-conti nuous format (cpha = 1, cont = 0) figure 42. example of continuous transfer (cpha = 1, cont = 1) figure 43. dspi pcs strobe (pcss ) timing 3.22.7 pdi timing table 65. pdi electrical characteristics no. symbol parameter conditions min max unit 1t pdi_clock sr pdi clock period ? 15 ? ns sck pcsx sck master sout master sin (cpol = 0) (cpol = 1) 2 2 3 13 sck pcs sck master sout master sin (cpol = 0) (cpol = 1) (cpol = 0) sck 3 2 2 pcsx 7 8 pcss
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 117 figure 44. pdi timing 3.22.8 fast ethernet interface mii signals use cmos signal levels compatible with devices oper ating at either 5.0 v or 3.3 v. signals are not ttl compatible. they follow the cmos elec trical characteristics. 3.22.8.1 mii receive signal timing (r xd[3:0], rx_dv, rx_er, and rx_clk) the receiver functions correctly up to a rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the sy stem clock frequency must exceed four times the rx_clk frequency. 2t pdi_is sr input setup time 1 ?3?ns 3t pdi_ih sr input hold time 1 ?3?ns 1 data can be captured at both launching and capturing edge of pdi_clk. table 66. mii receive signal timing no. parameter min max unit 1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5 ? ns 2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5 ? ns 3 rx_clk pulse width high 40% 60% rx_clk period 4 rx_clk pulse width low 40% 60% rx_clk period table 65. pdi electrical characteristics (continued) no. symbol parameter conditions min max unit pdi_clock 2 3 pdi_data[15:0] input data valid pdi_line_v pdi_frame_v 1
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 118 figure 45. mii receive signal timing diagram 3.22.8.2 mii transmit signal timing (txd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_clk maximu m frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the sy stem clock frequency must exceed four times the tx_clk frequency. the transmit outputs (txd[3:0], tx_en, tx_er) can be programme d to transition from either the rising or falling edge of tx_clk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for details of this option and how to enable it. figure 46. mii transmit signal timing diagram table 67. mii transmit signal timing 1 1 output pads configured with src = 0b11. no. parameter min max unit 5 tx_clk to txd[3:0], tx_en, tx_er invalid 5 ? ns 6 tx_clk to txd[3:0], tx_en, tx_er valid ? 25 ns 7 tx_clk pulse width high 40% 60% tx_clk period 8 tx_clk pulse width low 40% 60% tx_clk period 1 2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er 3 4 6 tx_clk (input) txd[3:0] (outputs) tx_en tx_er 5 7 8
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 119 3.22.8.3 mii async inputs signal timing (crs and col) figure 47. mii async inputs timing diagram 3.22.8.4 mii serial management channel timing (mdio and mdc) the fec functions correctly with a maximum mdc frequency of 5 mhz. table 68. mii async inputs signal timing 1 1 output pads configured with src = 0b11. no. parameter min max unit 9 crs, col minimum pulse width 1.5 ? tx_clk period table 69. mii serial management channel timing 1 1 output pads configured with src = 0b11. no. parameter min max unit 10 mdc falling edge to mdio output invalid (minimum propagation delay) 0 ? ns 11 mdc falling edge to mdio output valid (max prop delay) ? 25 ns 12 mdio (input) to mdc rising edge setup 10 ? ns 13 mdio (input) to mdc rising edge hold 0 ? ns 14 mdc pulse width high 40% 60% mdc period 15 mdc pulse width low 40% 60% mdc period crs, col 9
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 120 figure 48. mii serial management channel timing diagram 3.22.9 external bus interface (ebi) timing table 70. ebi timing no. symbol parameter 45 mhz (ext. bus freq) 1 unit notes min max 1t c cc d_clkout period 22.2 ? ns signals are measured at 50% v dde . 2t cdc cc d_clkout duty cycle 45% 55% t c ? 3t crt cc d_clkout rise time ? ? ns ? 4t cft cc d_clkout fall time ? ? ns ? 5t coh cc d_clkout posedge to output signal invalid or high z (hold time) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] 1.0 ? ns ? 11 mdc (output) mdio (output) 12 13 mdio (input) 10 14 15
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 121 6t cov cc d_clkout posedge to output signal valid (output delay) d_add[9:30] d_bdip d_cs[0:3] d_dat[0:15] d_oe d_rd_wr d_ta d_ts d_we [0:3]/d_be [0:3] ?10ns ? 7t cis cc input signal valid to d_clkout posedge (setup time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts 7.5 ? ns ? 8t cih cc d_clkout posedge to input signal invalid (hold time) d_add[9:30] d_dat[0:15] d_rd_wr d_ta d_ts 1.0 ? ns ? 9t apw cc d_ale pulse width 6.5 ? ns the timing is for asynchronous external memory system. 10 t aai cc d_ale negated to address invalid 1.5 ? ns ? the timing is for asynchronous external memory system. ? ale is measured at 50% of vdde. 1 speed is the nominal maximum frequency. maximum core speed allowed is 180 mhz plus frequency modulation (fm). table 70. ebi timing (continued) no. symbol parameter 45 mhz (ext. bus freq) 1 unit notes min max
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 122 figure 49. d_clkout timing figure 50. synchronous output timing 1 2 2 3 4 d_clkout v dde / 2 v ol_f v oh_f 6 5 5 d_clkout bus 5 output signal output v dde / 2 v dde / 2 v dde / 2 6 5 output signal v dde / 2 6
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 123 figure 51. synchronous input timing figure 52. ale signal timing 7 8 d_clkout input bus 7 8 input signal v dde / 2 v dde / 2 v dde / 2 ipg_clk d_clkout d_ale d_ts addr data d_add/d_dat 9 10
MPC5675K microcontroller data sheet, rev. 7 electrical characteristics freescale semiconductor 124 3.22.10 i 2 c timing table 71. i 2 c scl and sda input timing specifications no. symbol parameter value unit min max 1 ? d start condition ho ld time 2 ? ip bus cycle 1 1 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 ? d clock low time 8 ? ip bus cycle 1 3 ? d data hold time 0.0 ? ns 4 ? d clock high time 4 ? ip bus cycle 1 5 ? d data setup time 0.0 ? ns 6 ? d start condition setup time (for re peated start condition only) 2 ? ip bus cycle 1 7 ? d stop condition setup time 2 ? ip bus cycle 1 table 72. i 2 c scl and sda output timing specifications no. symbol parameter value unit min max 1 1 1 programming ibfd (i 2 c bus frequency divider) with the maximum frequency results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of the scl low period. the actual position is affected by the presca le and division values programmed in ifdr. ? d start condition hold time 6 ? ip bus cycle 2 2 inter peripheral clock is the clock at which the i 2 c peripheral is working in the device. 2 1 ? d clock low time 10 ? ip bus cycle 1 3 3 3 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on external signal capacitance and pullup resistor values. ? d scl/sda rise time ? 99.6 ns 4 1 ? d data hold time 7 ? ip bus cycle 1 5 1 ? d scl/sda fall time ? 99.5 ns 6 1 ? d clock high time 10 ? ip bus cycle 1 7 1 ? d data setup time 2 ? ip bus cycle 1 8 1 ? d start condition setup time (for repeated start condition only) 20 ? ip bus cycle 1 9 1 ? d stop condition setup time 10 ? ip bus cycle 1
electrical characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 125 figure 53. i 2 c input/output timing 3.22.11 linflex timing the maximum bit rate is 1.875 mbit/s. scl sda 1 2 3 4 5 6 7 8 9
MPC5675K microcontroller data sheet, rev. 7 package characteristics freescale semiconductor 126 4 package characteristics 4.1 package mechanical data 4.1.1 257 mapbga
package characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 127 figure 54. 257 mapbga mechanical data (1 of 2)
MPC5675K microcontroller data sheet, rev. 7 package characteristics freescale semiconductor 128 figure 55. 257 mapbga mechanical data (2 of 2)
package characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 129 4.1.2 473 mapbga figure 56. 473 mapbga package mechanical data (1 of 3)
MPC5675K microcontroller data sheet, rev. 7 package characteristics freescale semiconductor 130 figure 57. 473 mapbga package mechanical data (2 of 3)
package characteristics MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 131 figure 58. 473 mapbga package mechanical data (3 of 3)
MPC5675K microcontroller data sheet, rev. 7 orderable parts freescale semiconductor 132 5 orderable parts 6 reference documents 1. nexus (ieee-isto 5001??2008) 2. measurement of emission of ics?iec 61967-2 3. measurement of emission of ics?iec 61967-4 4. measurement of immunity of ics?iec 62132-4 5. semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 6. jedec specifications are avai lable at http://www.jedec.org 7. mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at 800-854-7179 or 303-397-7956. 8. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semi therm, san diego, 1998, pp. 47?54. 9. g. kromann, s. shidore, and s. addison, ?thermal mo deling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53?58, march 1998. 10. b. joiner and v. adams, ?measuremen t and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of se mitherm, san diego, 1999, pp. 212?220. 7 document revision history table 73 summarizes revisions to this document. beginning with rev. 4, this revision history uses clickable cr oss-references for ease of navigation. the numbers and titles in each cross-reference are relative to the latest published release. mpc f note: not all options are available on all devices. 5675k qualification status core code device number device feature set device revision temperature range v = ?40 c to 105 c device revision f0 = fab and mask operating frequency 1 = 150 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow f0 m temperature range mm package identifier 2 r operating frequency tape and reel status device feature set f=flexray package identifier mm = 257 bga 2 = 180 mhz m = ?40 c to 125 c ms= 473 bga (ambient)
document revision history MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 133 table 73. revision history revision date description of changes 1 6 oct 2009 initial release. 2 6 dec 2009 updated ball map tables, pin mu x tables, supply and system pin tables. added pmc specifications. 3 2 jul 2010 updated ball map tables, pin mu x tables, supply and system pin tables. updated pad specifications. added reset specifications section. 4 30 apr 2011 removed thickness dimension from package diagrams on cover page. added footnote ?do not connect pin directly to a power supply or ground? for mdo[0:15] and mseo[0:1] pins to table 9 (257 mapbga pin multiplexing) and table 10 (473 mapbga pin multiplexing) . in table 17 (pmc electrical specifications) : ? added minimum and maximum slew rate specifications for lvdreg. ? removed lvdc minimum and maximum hysteresis specifications ? removed hvdc minimum and maximum hysteresis specifications ? corrected hvcd nominal hysteresis from 1.32 to 1.36 in table 18 (vrc smps recommended external devices) , updated specifications for device q (fet). renamed section 3.9, supply current characteristics (was ?power dissipation and current consumption?). renamed table 19 (current consumption characteristics) (was ?power dissipation characteristics?). in table 19 (current consumption characteristics) : ? updated adc current consumption to 1.2 ma per adc plus 0.7 ma (2.0 ma total) for adc0. ? updated run i dd to 900 ma max. updated accuracy specification in table 20 (temperature sensor electrical characteristics) : changed ?t j = ?40 c to t a = 25 c? to ?t j = ?40 c to t a = 125 c,? removed row ?t j = t a to 125 c?. in table 21 (main oscillator electrical characteristics) , added symbol name f xoschs for oscillator frequency specification. removed ?typical? figures for these specifications. added footnote ?adc0 includes 0.7 ma dissipat ion for the temperature sensor (tsens).? in table 22 (fmpll electrical characteristics) , added minimum and maximum values for specification f free , ? free running frequency.? in table 23 (rc oscillator electrical characteristics) : ? added specification ? irctrim ? internal rc oscillator trimming step.? ? removed specification ? rctrim ? post trim accuracy: the variation of the ptf from the 16 mhz? (specification replaced by ? irctrim ? internal rc oscillator trimming step?). in table 24 (adc conversion characteristics), updated gain error (gne) to ?min = ?4 max = +4 lsb? . added table 30 (code flash write access timing) and table 31 (data flash write access timing) .
MPC5675K microcontroller data sheet, rev. 7 document revision history freescale semiconductor 134 5 6 dec 2011 editorial changes. enabled the use of cross-references in this revision-history table beginning with rev. 4. changed title of section 1, introduction (was ?overview?). added section headings: section 1.1, document overview , section 1.2, description in table 1 (MPC5675K family device comparison) : ? revised the dspi entry to reflect the proper number of chip selects on MPC5675K and mpc5674k. ? revised the flexray entry (was optional for all chips, is present on MPC5675K and optional on the others). ? deleted the ?clock output? entry. in figure 1 (MPC5675K block diagram) , added swt_0 and swt_1. in section 1.6.3, memory protection unit (mpu) , deleted "the memory protection unit splits the physical memory into 16 different regions." in section 1.6.11, dram controller , deleted ?ddr 2 (optional)?. revised section 1.6.14, deserial serial peripheral interface (dspi) modules , to reflect the accurate number of available chip selects. in section 1.6.16, flexcan , deleted ?safety can features on 1 can module as implemented on mpc5604p?. in table 17 (pmc electrical specifications) : ? removed min and max values for lvd 1.2 v variation at reset, lvd 1.2 v variation after reset, lvd 1.2 v hysteresis, hvd 1.2 v vari ation at reset, hvd 1.2 v variation after reset, and hvd 1.2 v hysteresis. ? updated nominal hvd 1.2 v typ value to 1.36 v. in table 18 (vrc smps recommended external devices) , updated the "part description", ?nominal?, and "description" columns for reference designator q. in table 22 (fmpll electrical characteristics) : ? updated f ref_crystal and f ref_ext min to 4 mhz; max to 120 mhz. for this spec, added footnote: ?pfd clock range is 4? 16 mhz. an appropriate idf should be chosen to divide the reference frequency to this range.? ? updated f pll_in min to 4 mhz; max to 16 mhz. ? updated f free min to 19 mhz; max to 60 mhz. ? updated t lpll max to 200 s. ? updated t dc min to 20%; max to 80%. ? updated c jitter max peak-to-peak to 160 ps; removed min. added footnote on condition: ?core operating at 180 mhz.? up dated long-term jitter max to 6 ns. ? updated f lck min to ?4%; max to +4%. ? updated f ul min to ?16%; max to +16%. ? updated modulation depth f cs min to 0.25%; max to 4%; f ds min to ?0.5%; max to ?8%. ? removed f mod min; updated max to 35 khz for ldf > 63; (2240/ldf)khz for 31 < ldf < 63. in table 23 (rc oscillator electrical characteristics) , changed the temperature in the condition for f rc (was 27 ? c, is 25 ? c). in table 24 (adc conversion characteristics) , changed the maximum specification for dnl (was 1.0 lsb, is 2 lsb). in section 3.18, pdi pads specifications : ? changed bullet ?vdd_hv_pdi range? to ?vdd_hv_pdi range 1.8 v to 3.3 v, as specified in the following tables? and removed sub-bullets. ? consolidated the three sets of dc and ac specifications (for 1.8 v, 2.5 v, and 3.3 v) into one set of specifications spanning the range 1.62?3.6 v. (section headers 3.18.1, 3.18.2, and 3.18.3 removed, and titles of table 36 (pdi pads dc electrical characteristics) , table 37 (drive current) , and table 38 (pdi pads ac electrical characteristics) changed.) table 73. revision history (continued) revision date description of changes
document revision history MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 135 5 (cont.) 6 dec 2011 in section 3.19, dram pad specifications , added the note ?0.7 v overshoot/undershoot can be allowed to occur repeatedly throughou t the product expected lifetime and will not cause any long term reliability issue.? in table 41 (dram pads dc electrical specifications (v dd_hv_dram = 3.3 v)) : ? updated v dd_hv_dram_vtt minimum value to v dd_hv_dram_vref ? 0.05 (changed ?? to ???) ? updated v il maximum value to v dd_hv_dram_vref ? 0.2 (changed ?? to ???) ? removed odt conditions for v oh and v ol . ? updated v ol maximum value to v dd_hv_dram_vtt ? 0.8 (changed ?? to ???) in table 44 (dram pads dc electrical specifications (v dd_hv_dram = 2.5 v)) , removed odt conditions for v oh and v ol . in table 47 (dram pads dc electrical specifications (v dd_hv_dram = 1.8 v)) : ? changed the minimum specification for v dd_hv_dram (was 1.7 v, is 1.62 v). ? removed odt conditions for v oh and v ol . ? updated v oh minimum value to 1.42 v ? updated v ol maximum value to 0.28 v added section 3.20.2, reset_sup_b pin characteristics . updated note under section 3.21.4.2, external vreg mode . updated figure 18 (external vreg mode, reset_sup rises after v dd_hv_xxx are stable) to add t rstsup . added section 3.22.2.1, standard interface timing , and revised the specifications in table 56 (jtag pin ac electrical characteristics) . added section 3.22.2.2, interface timing for full cycle mode . replaced the contents of section 3.22.3, nexus timing , with the following: ? table 58 (nexus debug port timing div mode = 2) and figure 29 (nexus sdr (even divisor) timing) ? table 59 (nexus debug port timing divide by 3 sdr mode) and figure 30 (nexus sdr output timing for div=3) ? table 60 (nexus debug port timing divide by 4 ddr mode) and figure 31 (nexus ddr mode timing) in section 5, orderable parts , updated the orderable part numbers. updated the entry for rev. 4 in this revision history. table 73. revision history (continued) revision date description of changes
MPC5675K microcontroller data sheet, rev. 7 document revision history freescale semiconductor 136 6 6 feb 2012 in section 1.5, feature list , removed ?replicated 32 channel edma controller? under ?interrupts?. in table 9 (257 mapbga pin multiplexing) , changed ?a2: ebi_d n ? to ?a2: ebi_ad n ? for balls h17, j17, k14, and k15. in table 10 (473 mapbga pin multiplexing) , changed ?a2: ebi_d n ? to ?a2: ebi_ad n ? for balls c22, d22, f21, f23, g 20, g21, g22, g23, h20, j20, j21, j22, j23, k21, k22, k23, m22, m23, n20, n21, n 22, n23, p20, p21, t20, t21, u21, v21, w21, y21, y22, and aa23. in table 11 (absolute maximum ratings) : ? removed ?incl. analog pins tbd? for i injpad . ? added numerical data to note 3. in table 17 (pmc electrical specifications) , added min/max information for lvdc and hvdc. in table 21 (main oscillator electrical characteristics) , split ?oscillator start-up time? into two lines and added numerical data. in table 22 (fmpll electrical characteristics) : ? added line numbers to table. ? changed tbd to ??? and added numerical data for f sys . ? changed tbds to numerical data for f lorl , f lorh , and f scm . ? changed tbd to ??? for c jitter . in table 24 (adc conversion characteristics) : ? changed t adc_e conditions from tbd to 60 mhz. ? changed c p2 max value from tbd to 0.8 pf. ? added a footnote to tue specs noting that sample averaging is required. ? changed tue min and max values from tbds to numerical data. ? changed thd min value from tbd to ?72 db. in table 25 (code flash memory program and erase electrical specifications) , ta bl e 2 6 (data flash memory program and er ase electrical specifications) , table 28 (code flash read access timing) and table 29 (data flash read access timing) , corrected the line numbering. in table 30 (code flash write access timing) : ? removed f write for 60 mhz. ? corrected the line numbering. ? changed tbd to ???. in table 31 (data flash write access timing) : ? removed f write for 60 mhz. ? corrected the line numbering. ? changed tbd to ???. in table 32 (system sram memory read/write access timing) : ? changed name from ?read access timing? to ?read/write access timing?. ? changed symbol to s read/write . ? removed s read/write for 60 mhz. removed table ?system sram me mory write access timing?. in table 36 (pdi pads dc electrical characteristics) , corrected the line numbering. in table 55 (ddr and ddr2 (ddr2-400) sdram timing specifications) : ? removed t dqsen and the associated footnotes. ? corrected the line numbering. in table 56 (jtag pin ac electrical characteristics) , corrected the line numbering. in table 61 (external interrupt timing (nmi irq)) : ? changed t ipwl min value from tbd to 3. ? changed t ipwh min value from tbd to 3. ? changed t icyc min value from tbd to 6. ? changed all units from ns to t cyc . table 73. revision history (continued) revision date description of changes
document revision history MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 137 6 (cont.) 6 feb 2012 in table 62 (external interrupt timing (gpio irq)) : ? changed t ipwl min value from tbd to 3. ? changed t ipwh min value from tbd to 3. ? changed t icyc min value from tbd to 6. ? changed all units from ns to t cyc . in table 71 (i 2 c scl and sda input timing specifications) , corrected the line numbering. 6.1 30 mar 2012 no content changes, technical or editorial, were made in this revision. change bars are identical to those in rev. 6. removed the ?preliminary? footers throughout. changed ?data sheet: advance information? to ?data sheet: technical data? on page 1. removed the ?product under development? disclaimer on page 1. 7 18 may 2012 minor editorial changes and improvements throughout. in section 1.3, device comparison , table 1 (MPC5675K family device comparison) , changed the cpu/data cache entry from "16 kb, 4-way with edc (sor)" to "16 kb, 4-way with parity (sor)". in section 1.3, device comparison , table 1 (MPC5675K family device comparison) , added footnotes to stipulate the peripheral instances that are used on derivative devices: ? added footnote to mpc5673k dspi module: ?d spi_0 and dspi_1.? ? added footnote to mpc5673k i2c module: ?i2c_0 and i2c_1.? ? added footnote to mpc5673k linflex module: ?linflex_0, linflex_1, and linflex_2? in section 1.4, block diagram : ? added missing modules (pmc, spe2, vle, and flash. ? added an arrow each from core_0 and core_1 to the xbar modules to represent the data path. ? updated the redundancy checkers to reflect the actual implementation. ? renamed the ?jtag/nexus? block to ?debug?, with jtag and nexus shown as submodules. in section 1.5, feature list , changed ?junction temperature sensor? to ?silicon substrate (die) temperature sensor?. in section 1.6.1, high-performance e200z7d core processor and section 1.6.9, cache memory , removed the bullet ?supports tag and data parity" and added the following bullets: ? supports tag and data cache parity ? supports edc for instruction cache in section 1.6.19, system timer module (stm) , changed ?duplicated periphery to guarantee that safety targets (sil3) are ac hieved? to ?replicated periphery to provide safety measures respective to high safety integrity levels (for example, sil 3, asil d)? in section 1.6.20.2, cross triggering unit (ctu) , changed ?dma support with safety features? to ?supports safety measures using dma?. in section 1.6.21, redundancy control and checker unit (rccu) , changed ?duplicated module to guarantee highest possible diagnostic coverage (check of checker)? to ?duplicated module to enable high diagnostic coverage (check of checker)?. in section 1.6.22, software watchdog timer (swt) , ? changed ?duplicated periphery to guarantee th at safety targets (si l3) are achieved? to ?replicated periphery to provide safety measures respective to high safety integrity levels (for example, sil 3, asil d)?. ? changed ?allows high level of safety (sil3 monitor)? to ?provides measures to target high safety integrity levels (for example, sil 3, asil d)?. in section 1.6.25, cyclic redundancy checker (crc) unit , in the sentence ?key engine to be coupled with communication periphery where crc application is added to allow implementation of safe communication protocol?, changed ?allow? to ?support?. table 73. revision history (continued) revision date description of changes
MPC5675K microcontroller data sheet, rev. 7 document revision history freescale semiconductor 138 7 (cont.) 18 may 2012 in section 3.2, absolute maximum ratings , table 11 (absolute maximum ratings) , ? deleted footnote to the max value ?absolute maximum voltages are currently maximum burn-in voltages. absolute maximum specifications for device stress have not yet been determined.? ? added footnote to v dd_hv_dram : ?as the v dd_hv_dram_vref supply should always be constrained by the v dd_hv_dram supply for example through a voltage divider network per the jedec specification, the maximum ratings for the v dd_hv_dram supply should be used for the v dd_hv_dram_vref reference as well.? ? changed absolute max rating for v dd_lv_pll from 1.4 to 1.32. ? added footnote to min value of t stg : ?if the ambient temperat ure is at or above the minimum storage temperature and below the recommended minimum operating temperature, power may be applied to the device safely. however, functionality is not guaranteed and a power cycle must be administered if in inte rnal regulation mode or an assertion of reset_sup_b must be administ ered if in external regulation mode once device enters into the recommended operating temperature range.? in section 3.3, recommended operating conditions , table 12 (recommended operating conditions) , ?for t a and t j, added footnote ?when determining if the operating temperature specifications are met, ei ther the ambient temperatur e or junction temperature specification can be used. it is not necessary that both s pecifications be met at all times. however, it is critical that the junc tion temperature specification is not exceeded under any condition.? ?for t a , changed the max temperature spec for the 257 package from 105 to 125 and deleted footnote: ?preliminary data.? in section 3.8.1, pmc electrical specifications , table 17 (pmc electrical specifications) , ? no. 4 lvdc and no. 5 hvdc threshold were specified as rising edge and hysteresis. the specification is changed to rising edge / falling edge. ? removed no. 6, vddstepc, an d renumbered subsequent lines. in section 3.9, supply current characteristics , table 19 (current consumption characteristics) , added a footnote to no. 3. idd_hv _fla. ?the current specified for idd_hv_fla includes current consumed during programming and erase operations.? in section 3.12, fmpll electrical characteristics , table 22 (fmpll electrical characteristics) , replaced ?f sys ? with ?f fmpllout ? in rows for c jitter , f lck , f ul , f cs /f ds , and footnote 9. in section 3.14.1, input impedance and adc accuracy : ? changed ?c s being substantially a swit ched capacitance...? to ?c s and c p2 being substantially a switched capacitance...? ? changed ?and the sum of r s + r f + r l + r sw + r ad , ...? to ?and the sum of r s + r f , ...? ? changed the equation to in section 3.14.1, input impedance and adc accuracy , table 24 (adc conversion characteristics) , added new spec after line 3 for t adc_s_pmc , c: parameter: sample time of internal pmc channels. conditions: - , min : 717, typ : - , max : - , unit : ns. in section 3.17.1, gp p ads dc specifications , table 33 (gp pads dc electrical characteristics , ) , added new spec for ?input pad capacitance?, no. 21. table 73. revision history (continued) revision date description of changes v a r s r f r l r sw r ad +++ + r eq -------------------------------------------------------------------------- - ? 1 2 -- -lsb ? v a r s r f + r eq --------------------- ? 1 2 -- -lsb ?
document revision history MPC5675K microcontrolle r data sheet, rev. 7 freescale semiconductor 139 7 (cont.) 18 may 2012 in section 3.18, pdi pads specifications , table 36 (pdi pads dc electrical characteristics) , added footnote to table: ?over- and undershoots occurring due to impedance mismatch of the external driver and the transmission line at pdi pads in input mode can be allowed up to 0.7 v repeatedly throughout the product expected lifetime and will not cause any long term reliability issue.? in section 5, orderable parts , ? removed ?3 = 220 mhz? under operating frequency heading and changed the operating frequency of the example from ?3? to ?2?. ? deleted table 73 (orderable part number summary ) . table 73. revision history (continued) revision date description of changes
document number: MPC5675K rev. 7 5/2012 information in this document is provid ed solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabr icate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or us e of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/freescale/docs/termsandconditions.htm how to reach us: home page: freescale.com web support: freescale.com/support freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, kinetis, mobilegt, powerquicc, processor expert, qoriq, qorivva, starcore, symphony, and vortiqa are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, coldfire+, corenet, flexis, magniv, mxc, platform in a package, qoriq qonverge, quicc engine, ready play, safeassure, smartmos , turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? 2009?2012 freescale semiconductor, inc.

▲Up To Search▲

Price & Availability of MPC5675K

	To Download MPC5675K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .